/freebsd/sys/contrib/device-tree/Bindings/pci/ |
H A D | altera-pcie.txt | 1 * Altera PCIe controller 4 - compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" 5 - reg: a list of physical base address and length for TXS and CRA. 6 For "altr,pcie-root-port-2.0", additional HIP base address and length. 7 - reg-names: must include the following entries: 8 "Txs": TX slave port region 10 "Hip": Hard IP region (if "altr,pcie-root-port-2.0") 11 - interrupts: specifies the interrupt source of the parent interrupt 14 - device_type: must be "pci" 15 - #address-cells: set to <3> [all …]
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H A D | altr,pcie-root-port.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/altr,pcie-root-port.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Altera PCIe Root Port 11 - Matthew Gerlach <matthew.gerlach@linux.intel.com> 16 - altr,pcie-root-port-1.0 17 - altr,pcie-root-port-2.0 21 - description: TX slave port region 22 - description: Control register access region [all …]
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H A D | nvidia,tegra20-pcie.txt | 1 NVIDIA Tegra PCIe controller 4 - compatible: Must be: 5 - "nvidia,tegra20-pcie": for Tegra20 6 - "nvidia,tegra30-pcie": for Tegra30 7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132 8 - "nvidia,tegra210-pcie": for Tegra210 9 - "nvidia,tegra186-pcie": for Tegra186 10 - power-domains: To ungate power partition by BPMP powergate driver. Must 11 contain BPMP phandle and PCIe power partition ID. This is required only 13 - device_type: Must be "pci" [all …]
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H A D | pci.txt | 3 PCI Bus Binding to: IEEE Std 1275-1994 4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf 9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf 14 - linux,pci-domain: 19 may be assigned to root buses behind different host bridges. The domain 21 - max-link-speed: 26 for gen2, and '1' for gen1. Any other values are invalid. 27 - reset-gpios: 30 - supports-clkreq: 32 root port to downstream device and host bridge drivers can do programming [all …]
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H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Synopsys DesignWare PCIe interface 10 - Jingoo Han <jingoohan1@gmail.com> 11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com> 14 Synopsys DesignWare PCIe host controller 16 # Please create a separate DT-schema for your DWC PCIe Root Port controller 17 # and make sure it's assigned with the vendor-specific compatible string. [all …]
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H A D | apple,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/apple,pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Apple PCIe host controller 10 - Mark Kettenis <kettenis@openbsd.org> 13 The Apple PCIe host controller is a PCIe host controller with 14 multiple root ports present in Apple ARM SoC platforms, including 16 The controller incorporates Synopsys DesigWare PCIe logic to 17 implements its root ports. But the ATU found on most DesignWare [all …]
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H A D | nvidia,tegra194-pcie.txt | 1 NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based) 3 This PCIe controller is based on the Synopsis Designware PCIe IP 4 and thus inherits all the common properties defined in snps,dw-pcie.yaml and 5 snps,dw-pcie-ep.yaml. 7 in root port mode or endpoint mode but one at a time. 10 - power-domains: A phandle to the node that controls power to the respective 11 PCIe controller and a specifier name for the PCIe controller. Following are 12 the specifiers for the different PCIe controllers 20 "include/dt-bindings/power/tegra194-powergate.h" file. 21 - reg: A list of physical base address and length pairs for each set of [all …]
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H A D | mediatek,mt7621-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MediaTek MT7621 PCIe controller 10 - Sergio Paracuellos <sergio.paracuellos@gmail.com> 13 MediaTek MT7621 PCIe subsys supports a single Root Complex (RC) 14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link 16 MT7621 PCIe HOST Topology 18 .-------. [all …]
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H A D | mobiveil-pcie.txt | 1 * Mobiveil AXI PCIe Root Port Bridge DT description 3 Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP 7 - #address-cells: Address representation for root ports, set to <3> 8 - #size-cells: Size representation for root ports, set to <2> 9 - #interrupt-cells: specifies the number of cells needed to encode an 10 interrupt source. The value must be 1. 11 - compatible: Should contain "mbvl,gpex40-pcie" 12 - reg: Should contain PCIe registers location and length 14 "config_axi_slave": PCIe controller registers 20 - device_type: must be "pci" [all …]
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H A D | baikal,bt1-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Baikal-T1 PCIe Root Port Controller 10 - Serge Semin <fancer.lancer@gmail.com> 13 Embedded into Baikal-T1 SoC Root Complex controller with a single port 14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured 15 to have just a single Root Port function and is capable of establishing the 18 performed by software. There four in- and four outbound iATU regions [all …]
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H A D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/snps,dw-pci [all...] |
H A D | mediatek-pcie.txt | 1 MediaTek Gen2 PCIe controller 4 - compatible: Should contain one of the following strings: 5 "mediatek,mt2701-pcie" 6 "mediatek,mt2712-pcie" 7 "mediatek,mt7622-pcie" 8 "mediatek,mt7623-pcie" 9 "mediatek,mt7629-pcie" 10 "airoha,en7523-pcie" 11 - device_type: Must be "pci" 12 - reg: Base addresses and lengths of the root ports. [all …]
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H A D | microchip,pcie-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip PCIe Root Port Bridge Controller 10 - Daire McNamara <daire.mcnamara@microchip.com> 13 - $ref: plda,xpressrich3-axi-common.yaml# 14 - $ref: /schemas/interrupt-controller/msi-controller.yaml# 18 const: microchip,pcie-host-1.0 # PolarFire 27 enabled for each of the interfaces the root port is connected through. [all …]
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H A D | xilinx-nwl-pcie.txt | 1 * Xilinx NWL PCIe Root Port Bridge DT description 4 - compatible: Should contain "xlnx,nwl-pcie-2.11" 5 - #address-cells: Address representation for root ports, set to <3> 6 - #size-cells: Size representation for root ports, set to <2> 7 - #interrupt-cells: specifies the number of cells needed to encode an 8 interrupt source. The value must be 1. 9 - reg: Should contain Bridge, PCIe Controller registers location, 11 - reg-names: Must include the following entries: 13 "pcireg": PCIe controller registers 15 - device_type: must be "pci" [all …]
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H A D | xilinx-pcie.txt | 1 * Xilinx AXI PCIe Root Port Bridge DT description 4 - #address-cells: Address representation for root ports, set to <3> 5 - #size-cells: Size representation for root ports, set to <2> 6 - #interrupt-cells: specifies the number of cells needed to encode an 7 interrupt source. The value must be 1. 8 - compatible: Should contain "xlnx,axi-pcie-host-1.00.a" 9 - reg: Should contain AXI PCIe registers location and length 10 - device_type: must be "pci" 11 - interrupts: Should contain AXI PCIe interrupt 12 - interrupt-map-mask, [all …]
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H A D | nvidia,tegra194-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based) 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Vidya Sagar <vidyas@nvidia.com> 15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus 16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of [all …]
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/freebsd/share/misc/ |
H A D | pci_vendors | 5 # Date: 2024-11-25 03:15:02 8 # the PCI ID Project at https://pci-ids.ucw.cz/. 14 # (version 2 or higher) or the 3-clause BSD License. 25 # device device_name <-- single tab 26 # subvendor subdevice subsystem_name <-- two tabs 30 # This is a relabelled RTL-8139 31 8139 AT-2500TX V3 Ethernet 41 7a09 PCI-to-PCI Bridge 50 7a19 PCI-to-PCI Bridge 55 7a29 PCI-to-PCI Bridge [all …]
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/freebsd/sys/contrib/device-tree/src/powerpc/ |
H A D | turris1x.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Turris 1.x Device Tree Source 5 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/) 8 * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/ 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/interrupt-controller/irq.h> 13 #include <dt-bindings/leds/common.h> 14 /include/ "fsl/p2020si-pre.dtsi" 17 model = "Turris 1.x"; 41 gpio-controller@18 { [all …]
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H A D | currituck.dts | 11 /dts-v1/; 16 #address-cells = <2>; 17 #size-cells = <2>; 20 dcr-parent = <&{/cpus/cpu@0}>; 27 #address-cells = <1>; 28 #size-cells = <0>; 34 clock-frequency = <1600000000>; // 1.6 GHz 35 timebase-frequency = <100000000>; // 100Mhz 36 i-cache-line-size = <32>; 37 d-cache-line-size = <32>; [all …]
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H A D | akebono.dts | 12 /dts-v1/; 17 #address-cells = <2>; 18 #size-cells = <2>; 21 dcr-parent = <&{/cpus/cpu@0}>; 28 #address-cells = <1>; 29 #size-cells = <0>; 35 clock-frequency = <1600000000>; // 1.6 GHz 36 timebase-frequency = <100000000>; // 100Mhz 37 i-cache-line-size = <32>; 38 d-cache-line-size = <32>; [all …]
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/freebsd/sys/contrib/alpine-hal/ |
H A D | al_hal_pcie_interrupts.h | 1 /*- 10 found at http://www.gnu.org/licenses/gpl-2.0.html 45 * @defgroup group_pcie_interrupts PCIe interrupts 48 * The PCIe interrupts HAL can be used to control PCIe unit interrupts. 50 * Only 2 interrupts go from the pcie unit to the GIC: 51 * 1. Summary for all the int groups (AXI+APP CORE). 62 * PCIe interrupt groups 73 * App group A interrupts mask - don't change 80 AL_PCIE_APP_INT_DEASSERT_INTC = AL_BIT(1), 84 * [RC only] Deassert_INTA received - there's a dedicated GIC interrupt [all …]
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H A D | al_hal_pcie.h | 1 /*- 10 found at http://www.gnu.org/licenses/gpl-2.0.html 41 * This header file provide API for the HAL driver of the pcie port, the driver 43 * - Port initialization 44 * - Link operation 45 * - Interrupts transactions generation (Endpoint mode). 46 * - Configuration Access management functions 47 * - Internal Translation Unit programming 50 * - PCIe transactions generation and reception (except interrupts as mentioned 51 * above) as this functionality is done by the port without need for sw [all …]
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/freebsd/sys/contrib/device-tree/Bindings/net/dsa/ |
H A D | ocelot.txt | 5 ----- 9 - VSC9959 (Felix) 10 - VSC9953 (Seville) 13 larger ENETC root complex. As a result, the ethernet-switch node is a sub-node 14 of the PCIe root complex node and its "reg" property conforms to the parent 17 * reg: Specifies PCIe Device Number and Function Number of the endpoint device, 25 For the external switch ports, depending on board configuration, "phy-mode" and 26 "phy-handle" are populated by board specific device tree instances. Ports 4 and 29 The CPU port property ("ethernet") configures the feature called "NPI port" in 30 the Ocelot hardware core. The CPU port in Ocelot is a set of queues, which are [all …]
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H A D | mscc,ocelot.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Vladimir Oltean <vladimir.oltean@nxp.com> 11 - Claudiu Manoil <claudiu.manoil@nxp.com> 12 - Alexandre Belloni <alexandre.belloni@bootlin.com> 13 - UNGLinuxDriver@microchip.com 16 There are multiple switches which are either part of the Ocelot-1 family, or 19 SPI or PCIe. The present DSA binding shall be used when the host controlling 20 them performs packet I/O primarily through an Ethernet port of the switch [all …]
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/freebsd/share/man/man4/ |
H A D | ntb_hw_plx.4 | 2 .\" Copyright (c) 2017-2019 Alexander Motin <mav@FreeBSD.org> 8 .\" 1. Redistributions of source code must retain the above copyright 31 .Nd PLX/Avago/Broadcom Non-Transparent Bridge driver 35 .Bd -ragged -offset indent 42 .Bd -literal -offset indent 48 .Bl -ohang 50 Being set to 1 (default) tells the driver attached to Virtual Interface of the 51 NTB that it works in NTB-to-NTB (back-to-back) mode, 0 -- NTB-to-Root Port. 52 Driver attached to Link Interface (visible from Root Port side) switches to 53 NTB-to-Root Port mode automatically, but one attached to Virtual Interface [all …]
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