1*c66ec88fSEmmanuel Vadot* Altera PCIe controller 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotRequired properties: 4*c66ec88fSEmmanuel Vadot- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" 5*c66ec88fSEmmanuel Vadot- reg: a list of physical base address and length for TXS and CRA. 6*c66ec88fSEmmanuel Vadot For "altr,pcie-root-port-2.0", additional HIP base address and length. 7*c66ec88fSEmmanuel Vadot- reg-names: must include the following entries: 8*c66ec88fSEmmanuel Vadot "Txs": TX slave port region 9*c66ec88fSEmmanuel Vadot "Cra": Control register access region 10*c66ec88fSEmmanuel Vadot "Hip": Hard IP region (if "altr,pcie-root-port-2.0") 11*c66ec88fSEmmanuel Vadot- interrupts: specifies the interrupt source of the parent interrupt 12*c66ec88fSEmmanuel Vadot controller. The format of the interrupt specifier depends 13*c66ec88fSEmmanuel Vadot on the parent interrupt controller. 14*c66ec88fSEmmanuel Vadot- device_type: must be "pci" 15*c66ec88fSEmmanuel Vadot- #address-cells: set to <3> 16*c66ec88fSEmmanuel Vadot- #size-cells: set to <2> 17*c66ec88fSEmmanuel Vadot- #interrupt-cells: set to <1> 18*c66ec88fSEmmanuel Vadot- ranges: describes the translation of addresses for root ports and 19*c66ec88fSEmmanuel Vadot standard PCI regions. 20*c66ec88fSEmmanuel Vadot- interrupt-map-mask and interrupt-map: standard PCI properties to define the 21*c66ec88fSEmmanuel Vadot mapping of the PCIe interface to interrupt numbers. 22*c66ec88fSEmmanuel Vadot 23*c66ec88fSEmmanuel VadotOptional properties: 24*c66ec88fSEmmanuel Vadot- msi-parent: Link to the hardware entity that serves as the MSI controller 25*c66ec88fSEmmanuel Vadot for this PCIe controller. 26*c66ec88fSEmmanuel Vadot- bus-range: PCI bus numbers covered 27*c66ec88fSEmmanuel Vadot 28*c66ec88fSEmmanuel VadotExample 29*c66ec88fSEmmanuel Vadot pcie_0: pcie@c00000000 { 30*c66ec88fSEmmanuel Vadot compatible = "altr,pcie-root-port-1.0"; 31*c66ec88fSEmmanuel Vadot reg = <0xc0000000 0x20000000>, 32*c66ec88fSEmmanuel Vadot <0xff220000 0x00004000>; 33*c66ec88fSEmmanuel Vadot reg-names = "Txs", "Cra"; 34*c66ec88fSEmmanuel Vadot interrupt-parent = <&hps_0_arm_gic_0>; 35*c66ec88fSEmmanuel Vadot interrupts = <0 40 4>; 36*c66ec88fSEmmanuel Vadot interrupt-controller; 37*c66ec88fSEmmanuel Vadot #interrupt-cells = <1>; 38*c66ec88fSEmmanuel Vadot bus-range = <0x0 0xFF>; 39*c66ec88fSEmmanuel Vadot device_type = "pci"; 40*c66ec88fSEmmanuel Vadot msi-parent = <&msi_to_gic_gen_0>; 41*c66ec88fSEmmanuel Vadot #address-cells = <3>; 42*c66ec88fSEmmanuel Vadot #size-cells = <2>; 43*c66ec88fSEmmanuel Vadot interrupt-map-mask = <0 0 0 7>; 44*c66ec88fSEmmanuel Vadot interrupt-map = <0 0 0 1 &pcie_0 1>, 45*c66ec88fSEmmanuel Vadot <0 0 0 2 &pcie_0 2>, 46*c66ec88fSEmmanuel Vadot <0 0 0 3 &pcie_0 3>, 47*c66ec88fSEmmanuel Vadot <0 0 0 4 &pcie_0 4>; 48*c66ec88fSEmmanuel Vadot ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000 49*c66ec88fSEmmanuel Vadot 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>; 50*c66ec88fSEmmanuel Vadot }; 51