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/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.h1 /* SPDX-License-Identifier: GPL-2.0+ */
46 #define EXYNOS_EINT_EDGE_FALLING 2
61 * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16]
75 #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ argument
79 .nr_pins = pins, \
84 #define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ argument
88 .nr_pins = pins, \
94 #define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ argument
98 .nr_pins = pins, \
104 #define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \ argument
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4 part and usage.
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
11 Available mpp pins/groups and functions:
12 Note: brackets (x) are not part of the mpp name for marvell,function and given
16 name pins functions
20 mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
23 uart1(cts), lcd-spi(cs1), pmu*
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H A Dsamsung,pinctrl-pins-cfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-pins-cfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC pin controller - pins configuration
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
18 Pins configuration for Samsung S3C/S5P/Exynos SoC pin controller.
[all …]
H A Dsprd,sc9860-pinctrl.txt3 Please refer to sprd,pinctrl.txt in this directory for common binding part
7 - compatible: Must be "sprd,sc9860-pinctrl".
8 - reg: The register address of pin controller device.
9 - pins : An array of strings, each string containing the name of a pin.
12 - function: A string containing the name of the function, values must be
14 - drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
16 - input-schmitt-disable: Enable schmitt-trigger mode.
17 - input-schmitt-enable: Disable schmitt-trigger mode.
18 - bias-disable: Disable pin bias.
19 - bias-pull-down: Pull down on pin.
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H A Dmarvell,orion-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4 part and usage.
7 - compatible: "marvell,88f5181-pinctrl",
8 "marvell,88f5181l-pinctrl",
9 "marvell,88f5182-pinctrl",
10 "marvell,88f5281-pinctrl"
12 - reg: two register areas, the first one describing the first two
16 Available mpp pins/groups and functions:
17 Note: brackets (x) are not part of the mpp name for marvell,function and given
22 name pins functions
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H A Dfsl,vf610-iomuxc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,vf610-iomuxc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
14 - Frank Li <Frank.Li@nxp.com>
18 const: fsl,vf610-iomuxc
31 fsl,pins:
33 two integers array, represents a group of pins mux and config setting.
34 The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a pin
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H A Drenesas,rza1-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
18 Each "port" features up to 16 pins, each of them configurable for GPIO
25 - const: renesas,r7s72100-ports # RZ/A1H
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H A Dfsl,imx7ulp-iomuxc1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx7ulp-iomuxc1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 Please refer to fsl,imx-pinctrl.txt in this directory for common binding
17 part and usage.
20 - Frank Li <Frank.Li@nxp.com>
24 const: fsl,imx7ulp-iomuxc1
37 fsl,pins:
43 imx7ulp-pinfunc.h in the device tree source folder.
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H A Dfsl,imx-pinctrl.txt10 Please refer to pinctrl-bindings.txt in this directory for details of the
14 Freescale IMX pin configuration node is a node of a group of pins which can be
16 of the pins in that group. The 'mux' selects the function mode(also named mux
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry
41 Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
[all …]
H A Dfsl,imxrt1050.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Giulio Benetti <giulio.benetti@benettiengineering.com>
11 - Jesse Taube <Mr.Bossman075@gmail.com>
14 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
15 for common binding part and usage.
19 const: fsl,imxrt1050-iomuxc
33 fsl,pins:
38 be found in <arch/arm/boot/dts/imxrt1050-pinfunc.h>. The last
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H A Dfsl,imxrt1170.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Giulio Benetti <giulio.benetti@benettiengineering.com>
11 - Jesse Taube <Mr.Bossman075@gmail.com>
14 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
15 for common binding part and usage.
19 const: fsl,imxrt1170-iomuxc
33 fsl,pins:
38 be found in <arch/arm/boot/dts/imxrt1170-pinfunc.h>. The last
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H A Dti,iodelay.txt4 for each pin. For most part the IO delay values are programmed by the bootloader,
5 but some pins need to be configured dynamically by the kernel such as the
6 MMC pins.
10 - compatible: Must be "ti,dra7-iodelay"
11 - reg: Base address and length of the memory resource used
12 - #address-cells: Number of address cells
13 - #size-cells: Size of cells
14 - #pinctrl-cells: Number of pinctrl cells, must be 2. See also
15 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
18 -------
[all …]
H A Dfsl,imx35-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx35-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
14 for common binding part and usage.
17 - $ref: pinctrl.yaml#
22 - enum:
23 - fsl,imx35-iomuxc
[all …]
H A Dfsl,imx8m-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx8m-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
14 for common binding part and usage.
19 - fsl,imx8mm-iomuxc
20 - fsl,imx8mn-iomuxc
21 - fsl,imx8mp-iomuxc
[all …]
H A Dfsl,imx9-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx9-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
14 for common binding part and usage.
17 - $ref: pinctrl.yaml#
22 - fsl,imx91-iomuxc
23 - fsl,imx93-iomuxc
[all …]
/linux/Documentation/driver-api/
H A Dpin-control.rst9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
23 can control PINs. It may be able to multiplex, bias, set load capacitance,
24 set drive strength, etc. for individual pins or groups of pins.
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
30 be sparse - i.e. there may be gaps in the space with numbers where no
[all …]
H A Ddpll.rst1 .. SPDX-License-Identifier: GPL-2.0
10 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
33 connected pins.
52 The number of pins per dpll vary, but usually multiple pins shall be
56 It is also possible to list all the pins that were registered in the
82 - ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device
83 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll
89 - ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid
91 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dlan966x-kontron-kswitch-d10-mmt.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Common part of the device tree for the Kontron KSwitch D10 MMT
6 /dts-v1/;
8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
16 stdout-path = "serial0:115200n8";
19 gpio-restart {
20 compatible = "gpio-restart";
21 pinctrl-0 = <&reset_pins>;
22 pinctrl-names = "default";
29 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
[all …]
/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dap80x-system-controller.txt6 registers giving access to numerous features: clocks, pin-muxing and
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
18 -------
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be one of:
32 * "marvell,ap806-clock"
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx95-tqma9596sa.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2024 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 /dts-v1/;
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include <dt-bindings/usb/pd.h>
30 reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dorion5x-maxtor-shared-storage-2.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include "orion5x-mv88f5182.dtsi"
16 compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x";
25 stdout-path = &uart0;
34 gpio-keys {
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H A Dorion5x-lacie-d2-network.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include "orion5x-mv88f5182.dtsi"
16 compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x";
25 stdout-path = &uart0;
34 gpio-keys {
[all …]
H A Darmada-385-linksys.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include "armada-385.dtsi"
18 stdout-path = "serial0:115200n8";
34 usb3_1_phy: usb3_1-phy {
35 compatible = "usb-nop-xceiv";
36 vcc-supply = <&usb3_1_vbus>;
37 #phy-cells = <0>;
40 usb3_1_vbus: usb3_1-vbus {
[all …]
H A Darmada-xp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 #include "armada-370-xp.dtsi"
19 #address-cells = <2>;
20 #size-cells = <2>;
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
38 internal-regs {
40 compatible = "marvell,armada-xp-sdram-controller";
[all …]
/linux/Documentation/netlink/specs/
H A Ddpll.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 ---
8 -
16 -
20 -
23 render-max: true
24 -
26 name: lock-status
31 -
37 -
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