Lines Matching +full:part +full:- +full:2 +full:- +full:pins
1 .. SPDX-License-Identifier: GPL-2.0
10 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
33 connected pins.
52 The number of pins per dpll vary, but usually multiple pins shall be
56 It is also possible to list all the pins that were registered in the
82 - ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device
83 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll
89 - ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid
91 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as
98 Shared pins
104 1) Set on a pin - the configuration affects all dpll devices pin is
106 2) Set on a pin-dpll tuple - the configuration affects only selected
110 MUX-type pins
113 A pin can be MUX-type, it aggregates child pins and serves as a pin
114 multiplexer. One or more pins are registered with MUX-type instead of
116 Pins registered with a MUX-type pin provide user with additional nested
119 If a pin was registered with multiple parent pins, they behave like a
121 ``DPLL_CMD_PIN_GET`` would contain multiple pin-parent nested
125 'clock-id': 282574471561216,
126 'module-name': 'ice',
129 'parent-pin': [
130 {'parent-id': 2, 'state': 'connected'},
131 {'parent-id': 3, 'state': 'disconnected'}
133 'type': 'synce-eth-port'
136 Only one child pin can provide its signal to the parent MUX-type pin at
155 means only pins directly connected to the dpll can be used for automatic
159 connected pins with a priority ``DPLL_A_PIN_PRIO``, the device would
171 Child pin of MUX-type pin is not capable of automatic input pin selection,
172 in order to configure active input of a MUX-type pin, the user needs to
174 as described in the ``MUX-type pins`` chapter.
180 on a pin and its parent dpll device. If pin-dpll phase offset measurement
213 offset values are fractional with 3-digit decimal places and shell be
214 divided with ``DPLL_PIN_PHASE_OFFSET_DIVIDER`` to get integer part and
215 modulo divided to get fractional part.
221 source. However, some DPLL (Digital Phase-Locked Loop) devices may offer
239 to embed additional SYNC signal into the base frequency of a pin - a one
264 enables the provision of a high-quality loop bandwidth signal from an external
285 dpll devices (and pins), as well as set configuration of device or pins.
305 (EUI-64), as defined by the
316 (EUI-64), as defined by the
331 Constants identifying command types for pins uses a
340 (EUI-64), as defined by the
353 list of available pins
357 (EUI-64), as defined by the
397 ``DPLL_CMD_PIN_SET`` command to set pins configuration
428 ``DPLL_CMD_DEVICE_SET`` - to target a dpll device, the user provides
432 ``DPLL_CMD_PIN_SET`` - to target a pin user must provide a
443 For MUX-type pins the ``DPLL_A_PIN_STATE`` attribute is configured in
451 Configuration pre-defined enums
454 .. kernel-doc:: include/uapi/linux/dpll.h
461 There is one multicast group that is used to notify user-space apps via
498 The pins are allocated separately with dpll_pin_get(), it works
507 - dpll_pin_register() - register pin with a dpll device,
508 - dpll_pin_on_pin_register() - register pin with another MUX type pin.
512 Notifications about registering/deregistering pins are also invoked by
517 - after successful change was requested on dpll subsystem, the subsystem
519 - requested by device driver with dpll_device_change_ntf() or
527 - ``.mode_get``,
528 - ``.lock_status_get``.
532 - ``.state_on_dpll_get`` (pins registered with dpll device),
533 - ``.state_on_pin_get`` (pins registered with parent pin),
534 - ``.direction_get``.
537 ``-EOPNOTSUPP`` is returned in case of absence of specific handler.
542 .. code-block:: c
558 The registration part is then looks like this part:
560 .. code-block:: c
563 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE);
564 if (IS_ERR(bp->dpll)) {
565 err = PTR_ERR(bp->dpll);
566 dev_err(&pdev->dev, "dpll_device_alloc failed\n");
570 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);
575 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop);
576 if (IS_ERR(bp->sma[i].dpll_pin)) {
577 err = PTR_ERR(bp->dpll);
581 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,
582 &bp->sma[i]);
584 dpll_pin_put(bp->sma[i].dpll_pin);
591 .. code-block:: c
594 --i;
595 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
596 dpll_pin_put(bp->sma[i].dpll_pin);
598 dpll_device_put(bp->dpll);
610 This is done by exposing a pin to the netdevice - attaching pin to the