Searched +full:odmi +full:- +full:controller (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,odmi-controller.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Marvell ODMI controller10 - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>13 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller which can14 be used by on-board peripherals for MSI interrupts.18 const: marvell,odmi-controller21 description: List of register definitions, one for each ODMI frame.[all …]
4 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>11 #define pr_fmt(fmt) "GIC-ODMI: " fmt21 #include <linux/irqchip/irq-msi-lib.h>23 #include <dt-bindings/interrupt-controller/arm-gic.h>38 #define NODMIS_MASK (NODMIS_PER_FRAME - 1)55 struct odmi_data *odmi; in odmi_compose_msi_msg() local59 if (WARN_ON(d->hwirq >= odmis_count * NODMIS_PER_FRAME)) in odmi_compose_msi_msg()62 odmi = &odmis[d->hwirq >> NODMIS_SHIFT]; in odmi_compose_msi_msg()63 odmin = d->hwirq & NODMIS_MASK; in odmi_compose_msi_msg()65 addr = odmi->res.start + GICP_ODMIN_SET; in odmi_compose_msi_msg()[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/thermal/thermal.h>11 /dts-v1/;14 #address-cells = <2>;15 #size-cells = <2>;25 compatible = "arm,psci-0.2";29 reserved-memory {30 #address-cells = <2>;31 #size-cells = <2>;[all …]