Lines Matching +full:odmi +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,odmi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell ODMI controller
10 - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller which can
14 be used by on-board peripherals for MSI interrupts.
18 const: marvell,odmi-controller
21 description: List of register definitions, one for each ODMI frame.
23 msi-controller: true
25 marvell,odmi-frames:
26 description: Number of ODMI frames available. Each frame provides a number of events.
29 marvell,spi-base:
31 List of GIC base SPI interrupts, one for each ODMI frame. Those SPI
32 interrupts are 0-based, i.e. marvell,spi-base = <128> will use SPI #96.
33 See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
35 $ref: /schemas/types.yaml#/definitions/uint32-array
38 - compatible
39 - reg
40 - msi-controller
41 - marvell,odmi-frames
42 - marvell,spi-base
47 - |
48 msi-controller@300000 {
49 compatible = "marvell,odmi-controller";
50 msi-controller;
51 marvell,odmi-frames = <4>;
53 marvell,spi-base = <128>, <136>, <144>, <152>;