| /linux/drivers/usb/host/ |
| H A D | octeon-hcd.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
102 * Core AHB Configuration Register (GAHBCFG)
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
107 * core. In general, software need not know about this interface except to
110 * The application must program this register as part of the O2P USB core
120 * Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
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| /linux/tools/perf/pmu-events/arch/x86/broadwell/ |
| H A D | uncore-interconnect.json | 3 …"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture,…
12 …Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0…
21 … waiting for data return from memory controller. Account for coherent and non-coherent requests in…
31 …de. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0)…
36 …de. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0)…
41 …"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and no…
50 … "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
55 … "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
60 …"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and…
|
| /linux/tools/perf/pmu-events/arch/x86/alderlaken/ |
| H A D | cache.json | 3 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
7 …ejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.",
11 …ion": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
15 …rom a front door request only (does not include rejects or recycles), Counts on a per core basis.",
20 …on": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.",
24 …rom a front door request only (does not include rejects or recycles). Counts on a per core basis.",
29 …"Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
33 … HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is th…
38 … "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
42 … HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is th…
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| /linux/tools/perf/pmu-events/arch/x86/amdzen3/ |
| H A D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
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| /linux/Documentation/driver-api/ |
| H A D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
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| /linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | other.json | 3 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
7 …Core cycles where the core was running with power-delivery for baseline license level 0. This inc…
12 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
16 …Core cycles where the core was running with power-delivery for license level 1. This includes hig…
21 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
25 …Core cycles where the core was running with power-delivery for license level 2 (introduced in Skyl…
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| /linux/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| H A D | cache.json | 3 …"BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by th…
7 …core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely …
24 … The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L…
28 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
32 …ejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.",
36 …ion": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
40 …rom a front door request only (does not include rejects or recycles), Counts on a per core basis.",
45 …on": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.",
49 …rom a front door request only (does not include rejects or recycles). Counts on a per core basis.",
54 …ts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.",
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| /linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | cache.json | 3 …"BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by th…
7 …core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely …
24 … The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L…
28 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
32 …ejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.",
36 …ion": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
40 …rom a front door request only (does not include rejects or recycles), Counts on a per core basis.",
45 …on": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.",
49 …rom a front door request only (does not include rejects or recycles). Counts on a per core basis.",
54 …ts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.",
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| /linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | other.json | 3 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
7 …Core cycles where the core was running with power-delivery for baseline license level 0. This inc…
12 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
16 …Core cycles where the core was running with power-delivery for license level 1. This includes hig…
21 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
25 …Core cycles where the core was running with power-delivery for license level 2 (introduced in Skyl…
30 … "BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
34 …"PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power lev…
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| /linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | other.json | 3 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
7 …Core cycles where the core was running with power-delivery for baseline license level 0. This inc…
12 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
16 …Core cycles where the core was running with power-delivery for license level 1. This includes hig…
21 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
25 …Core cycles where the core was running with power-delivery for license level 2 (introduced in Skyl…
30 …"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hav…
|
| /linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | other.json | 3 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
7 …Core cycles where the core was running with power-delivery for baseline license level 0. This inc…
12 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
16 …Core cycles where the core was running with power-delivery for license level 1. This includes hig…
21 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
25 …Core cycles where the core was running with power-delivery for license level 2 (introduced in Skyl…
30 …"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hav…
|
| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | other.json | 3 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
7 …Core cycles where the core was running with power-delivery for baseline license level 0. This inc…
12 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
16 …Core cycles where the core was running with power-delivery for license level 1. This includes hig…
21 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
25 …Core cycles where the core was running with power-delivery for license level 2 (introduced in Skyl…
30 …"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hav…
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen1/ |
| H A D | cache.json | 5 …etch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cachea…
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …ache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other threa…
64 …ache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other threa…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
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| /linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
| H A D | uncore-cache.json | 3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
12 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
21 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
30 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
39 …Description": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
48 …BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
57 …BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
66 …efDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
75 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
84 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
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| /linux/tools/perf/pmu-events/arch/x86/sandybridge/ |
| H A D | uncore-cache.json | 3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
12 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
21 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
30 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
39 …Description": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
48 …BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
57 …BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
66 …efDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
75 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
84 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
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| /linux/arch/arm/mach-omap2/ |
| H A D | omap-headsmp.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2014 Texas Instruments, Inc.
21 /* Physical address needed since MMU not enabled yet on secondary core */
38 * secondary core is held until we're ready for it to initialise.
39 * The primary core will update this flag using a hardware
58 .arch armv7-a
77 * secondary core is held until we're ready for it to initialise.
78 * The primary core will update this flag using a hardware
93 * should now contain the SVC stack for this core
113 * bit 1 == Non-Secure Enable
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| /linux/tools/perf/pmu-events/arch/x86/haswell/ |
| H A D | uncore-cache.json | 3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
12 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
21 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
30 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
39 …Description": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
48 …BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
57 …BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
66 …efDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
75 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
84 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
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| H A D | uncore-interconnect.json | 13 …"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture,…
22 …Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0…
31 … waiting for data return from memory controller. Account for coherent and non-coherent requests in…
41 …"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and no…
50 …"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and…
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen2/ |
| H A D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
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| /linux/drivers/cpuidle/ |
| H A D | cpuidle-cps.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <asm/pm-cps.h>
17 STATE_NC_WAIT, /* MIPS wait instruction, non-coherent */
18 STATE_CLOCK_GATED, /* Core clock gated */
19 STATE_POWER_GATED, /* Core power gated */
30 * At least one core must remain powered up & clocked in order for the in cps_nc_enter()
33 * TODO: don't treat core 0 specially, just prevent the final core in cps_nc_enter()
36 if (cpus_are_siblings(0, dev->cpu) && (index > STATE_NC_WAIT)) in cps_nc_enter()
52 return -EINVAL; in cps_nc_enter()
57 return -EINTR; in cps_nc_enter()
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| /linux/Documentation/arch/x86/ |
| H A D | topology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
35 - packages
36 - cores
37 - threads
48 Package-related topology information in the kernel:
50 - topology_num_threads_per_package()
54 - topology_num_cores_per_package()
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| /linux/drivers/nvdimm/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "NVDIMM (Non-Volatile Memory Device) Support"
9 Generic support for non-volatile memory devices including
10 ACPI-6-NFIT defined resources. On platforms that define an
28 non-standard OEM-specific E820 memory type (type-12, see
31 Documentation/admin-guide/kernel-parameters.rst). This driver converts
33 capable of DAX (direct-access) file system mappings. See
34 Documentation/driver-api/nvdimm/nvdimm.rst for more details.
69 management sub-system. By default persistent memory does
85 sub-divide a namespace into character devices that can only be
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| /linux/tools/perf/pmu-events/arch/x86/lunarlake/ |
| H A D | other.json | 3 …sed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicat…
7 …-AVX mix and A/D assists who are counted by dedicated sub-events. This includes, but not limited …
22 …n": "Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by an…
26 … the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another core.…
32 …unts the number of unhalted cycles a Core is blocked due to an Accepted lock it issued, includes b…
36 …nhalted cycles a Core is blocked due to an Accepted lock it issued, includes both split and non-sp…
42 …"BriefDescription": "Counts the number of non-split locks such as UC locks issued by a Core (does …
51 "BriefDescription": "Counts the number of split locks issued by a Core",
170 …urther requests (for example prefetches, loads or stores initiated by the Core that miss the L2 ca…
|
| /linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | cache.json | 16 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
68 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u…
105 "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache.",
109 …ropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event.",
125 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
129 …ejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.",
138 …"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excl…
144 …ion": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
148 …rom a front door request only (does not include rejects or recycles), Counts on a per core basis.",
154 …on": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.",
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| /linux/Documentation/misc-devices/ |
| H A D | xilinx_sdfec.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
4 Xilinx SD-FEC Driver
10 This driver supports SD-FEC Integrated Block for Zynq |Ultrascale+ (TM)| RFSoCs.
15 …f SD-FEC core features, see the `SD-FEC Product Guide (PG256) <https://www.xilinx.com/cgi-bin/docs…
19 - Retrieval of the Integrated Block configuration and status information
20 - Configuration of LDPC codes
21 - Configuration of Turbo decoding
22 - Monitoring errors
24 Missing features, known issues, and limitations of the SD-FEC driver are as
27 - Only allows a single open file handler to any instance of the driver at any time
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|