17e74ece3SIan Rogers[ 27e74ece3SIan Rogers { 37e74ece3SIan Rogers "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 4*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 57e74ece3SIan Rogers "EventCode": "0x28", 67e74ece3SIan Rogers "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", 77e74ece3SIan Rogers "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", 87e74ece3SIan Rogers "SampleAfterValue": "200003", 97e74ece3SIan Rogers "UMask": "0x7" 107e74ece3SIan Rogers }, 117e74ece3SIan Rogers { 127e74ece3SIan Rogers "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", 13*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 147e74ece3SIan Rogers "EventCode": "0x28", 157e74ece3SIan Rogers "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", 167e74ece3SIan Rogers "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", 177e74ece3SIan Rogers "SampleAfterValue": "200003", 187e74ece3SIan Rogers "UMask": "0x18" 197e74ece3SIan Rogers }, 207e74ece3SIan Rogers { 217e74ece3SIan Rogers "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", 22*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 237e74ece3SIan Rogers "EventCode": "0x28", 247e74ece3SIan Rogers "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", 258972c033SIan Rogers "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.", 267e74ece3SIan Rogers "SampleAfterValue": "200003", 277e74ece3SIan Rogers "UMask": "0x20" 287e74ece3SIan Rogers }, 297e74ece3SIan Rogers { 307e74ece3SIan Rogers "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", 31*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 327e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 337e74ece3SIan Rogers "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", 347e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 357e74ece3SIan Rogers "MSRValue": "0x10004", 367e74ece3SIan Rogers "SampleAfterValue": "100003", 377e74ece3SIan Rogers "UMask": "0x1" 387e74ece3SIan Rogers }, 397e74ece3SIan Rogers { 407e74ece3SIan Rogers "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", 41*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 427e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 437e74ece3SIan Rogers "EventName": "OCR.DEMAND_CODE_RD.DRAM", 447e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 457e74ece3SIan Rogers "MSRValue": "0x184000004", 467e74ece3SIan Rogers "SampleAfterValue": "100003", 477e74ece3SIan Rogers "UMask": "0x1" 487e74ece3SIan Rogers }, 497e74ece3SIan Rogers { 507e74ece3SIan Rogers "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", 51*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 527e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 537e74ece3SIan Rogers "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", 547e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 557e74ece3SIan Rogers "MSRValue": "0x184000004", 567e74ece3SIan Rogers "SampleAfterValue": "100003", 577e74ece3SIan Rogers "UMask": "0x1" 587e74ece3SIan Rogers }, 597e74ece3SIan Rogers { 607e74ece3SIan Rogers "BriefDescription": "Counts demand data reads that have any type of response.", 61*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 627e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 637e74ece3SIan Rogers "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 647e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 657e74ece3SIan Rogers "MSRValue": "0x10001", 667e74ece3SIan Rogers "SampleAfterValue": "100003", 677e74ece3SIan Rogers "UMask": "0x1" 687e74ece3SIan Rogers }, 697e74ece3SIan Rogers { 707e74ece3SIan Rogers "BriefDescription": "Counts demand data reads that DRAM supplied the request.", 71*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 727e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 737e74ece3SIan Rogers "EventName": "OCR.DEMAND_DATA_RD.DRAM", 747e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 757e74ece3SIan Rogers "MSRValue": "0x184000001", 767e74ece3SIan Rogers "SampleAfterValue": "100003", 777e74ece3SIan Rogers "UMask": "0x1" 787e74ece3SIan Rogers }, 797e74ece3SIan Rogers { 807e74ece3SIan Rogers "BriefDescription": "Counts demand data reads that DRAM supplied the request.", 81*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 827e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 837e74ece3SIan Rogers "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", 847e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 857e74ece3SIan Rogers "MSRValue": "0x184000001", 867e74ece3SIan Rogers "SampleAfterValue": "100003", 877e74ece3SIan Rogers "UMask": "0x1" 887e74ece3SIan Rogers }, 897e74ece3SIan Rogers { 907e74ece3SIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 91*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 927e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 937e74ece3SIan Rogers "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 947e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 957e74ece3SIan Rogers "MSRValue": "0x10002", 967e74ece3SIan Rogers "SampleAfterValue": "100003", 977e74ece3SIan Rogers "UMask": "0x1" 987e74ece3SIan Rogers }, 997e74ece3SIan Rogers { 1007e74ece3SIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", 101*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 1027e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 1037e74ece3SIan Rogers "EventName": "OCR.DEMAND_RFO.DRAM", 1047e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 1057e74ece3SIan Rogers "MSRValue": "0x184000002", 1067e74ece3SIan Rogers "SampleAfterValue": "100003", 1077e74ece3SIan Rogers "UMask": "0x1" 1087e74ece3SIan Rogers }, 1097e74ece3SIan Rogers { 1107e74ece3SIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", 111*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 1127e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 1137e74ece3SIan Rogers "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", 1147e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 1157e74ece3SIan Rogers "MSRValue": "0x184000002", 1167e74ece3SIan Rogers "SampleAfterValue": "100003", 1177e74ece3SIan Rogers "UMask": "0x1" 1187e74ece3SIan Rogers }, 1197e74ece3SIan Rogers { 1207e74ece3SIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", 121*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 1227e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 1237e74ece3SIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", 1247e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 1257e74ece3SIan Rogers "MSRValue": "0x10400", 1267e74ece3SIan Rogers "SampleAfterValue": "100003", 1277e74ece3SIan Rogers "UMask": "0x1" 1287e74ece3SIan Rogers }, 1297e74ece3SIan Rogers { 1307e74ece3SIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", 131*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 1327e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 1337e74ece3SIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", 1347e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 1357e74ece3SIan Rogers "MSRValue": "0x184000400", 1367e74ece3SIan Rogers "SampleAfterValue": "100003", 1377e74ece3SIan Rogers "UMask": "0x1" 1387e74ece3SIan Rogers }, 1397e74ece3SIan Rogers { 1407e74ece3SIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", 141*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 1427e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 1437e74ece3SIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", 1447e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 1457e74ece3SIan Rogers "MSRValue": "0x184000400", 1467e74ece3SIan Rogers "SampleAfterValue": "100003", 1477e74ece3SIan Rogers "UMask": "0x1" 1487e74ece3SIan Rogers }, 1497e74ece3SIan Rogers { 1507e74ece3SIan Rogers "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", 151*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 1527e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 1537e74ece3SIan Rogers "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", 1547e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 1557e74ece3SIan Rogers "MSRValue": "0x10010", 1567e74ece3SIan Rogers "SampleAfterValue": "100003", 1577e74ece3SIan Rogers "UMask": "0x1" 1587e74ece3SIan Rogers }, 1597e74ece3SIan Rogers { 1607e74ece3SIan Rogers "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", 161*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 1627e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 1637e74ece3SIan Rogers "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", 1647e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 1657e74ece3SIan Rogers "MSRValue": "0x184000010", 1667e74ece3SIan Rogers "SampleAfterValue": "100003", 1677e74ece3SIan Rogers "UMask": "0x1" 1687e74ece3SIan Rogers }, 1697e74ece3SIan Rogers { 1707e74ece3SIan Rogers "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", 171*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 1727e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 1737e74ece3SIan Rogers "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", 1747e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 1757e74ece3SIan Rogers "MSRValue": "0x184000010", 1767e74ece3SIan Rogers "SampleAfterValue": "100003", 1777e74ece3SIan Rogers "UMask": "0x1" 1787e74ece3SIan Rogers }, 1797e74ece3SIan Rogers { 1807e74ece3SIan Rogers "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.", 181*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 1827e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 1837e74ece3SIan Rogers "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", 1847e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 1857e74ece3SIan Rogers "MSRValue": "0x10020", 1867e74ece3SIan Rogers "SampleAfterValue": "100003", 1877e74ece3SIan Rogers "UMask": "0x1" 1887e74ece3SIan Rogers }, 1897e74ece3SIan Rogers { 1907e74ece3SIan Rogers "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", 191*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 1927e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 1937e74ece3SIan Rogers "EventName": "OCR.HWPF_L2_RFO.DRAM", 1947e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 1957e74ece3SIan Rogers "MSRValue": "0x184000020", 1967e74ece3SIan Rogers "SampleAfterValue": "100003", 1977e74ece3SIan Rogers "UMask": "0x1" 1987e74ece3SIan Rogers }, 1997e74ece3SIan Rogers { 2007e74ece3SIan Rogers "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", 201*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 2027e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 2037e74ece3SIan Rogers "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", 2047e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 2057e74ece3SIan Rogers "MSRValue": "0x184000020", 2067e74ece3SIan Rogers "SampleAfterValue": "100003", 2077e74ece3SIan Rogers "UMask": "0x1" 2087e74ece3SIan Rogers }, 2097e74ece3SIan Rogers { 2107e74ece3SIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", 211*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 2127e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 2137e74ece3SIan Rogers "EventName": "OCR.OTHER.ANY_RESPONSE", 2147e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 2157e74ece3SIan Rogers "MSRValue": "0x18000", 2167e74ece3SIan Rogers "SampleAfterValue": "100003", 2177e74ece3SIan Rogers "UMask": "0x1" 2187e74ece3SIan Rogers }, 2197e74ece3SIan Rogers { 2207e74ece3SIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", 221*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 2227e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 2237e74ece3SIan Rogers "EventName": "OCR.OTHER.DRAM", 2247e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 2257e74ece3SIan Rogers "MSRValue": "0x184008000", 2267e74ece3SIan Rogers "SampleAfterValue": "100003", 2277e74ece3SIan Rogers "UMask": "0x1" 2287e74ece3SIan Rogers }, 2297e74ece3SIan Rogers { 2307e74ece3SIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", 231*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 2327e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 2337e74ece3SIan Rogers "EventName": "OCR.OTHER.LOCAL_DRAM", 2347e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 2357e74ece3SIan Rogers "MSRValue": "0x184008000", 2367e74ece3SIan Rogers "SampleAfterValue": "100003", 2377e74ece3SIan Rogers "UMask": "0x1" 2387e74ece3SIan Rogers }, 2397e74ece3SIan Rogers { 2407e74ece3SIan Rogers "BriefDescription": "Counts streaming stores that have any type of response.", 241*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 2427e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 2437e74ece3SIan Rogers "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 2447e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 2457e74ece3SIan Rogers "MSRValue": "0x10800", 2467e74ece3SIan Rogers "SampleAfterValue": "100003", 2477e74ece3SIan Rogers "UMask": "0x1" 2487e74ece3SIan Rogers }, 2497e74ece3SIan Rogers { 2507e74ece3SIan Rogers "BriefDescription": "Counts streaming stores that DRAM supplied the request.", 251*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 2527e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 2537e74ece3SIan Rogers "EventName": "OCR.STREAMING_WR.DRAM", 2547e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 2557e74ece3SIan Rogers "MSRValue": "0x184000800", 2567e74ece3SIan Rogers "SampleAfterValue": "100003", 2577e74ece3SIan Rogers "UMask": "0x1" 2587e74ece3SIan Rogers }, 2597e74ece3SIan Rogers { 2607e74ece3SIan Rogers "BriefDescription": "Counts streaming stores that DRAM supplied the request.", 261*bf0dd1f4SIan Rogers "Counter": "0,1,2,3", 2627e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 2637e74ece3SIan Rogers "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", 2647e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 2657e74ece3SIan Rogers "MSRValue": "0x184000800", 2667e74ece3SIan Rogers "SampleAfterValue": "100003", 2677e74ece3SIan Rogers "UMask": "0x1" 2687e74ece3SIan Rogers } 2697e74ece3SIan Rogers] 270