Searched full:muxable (Results 1 – 9 of 9) sorted by relevance
| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap3-gta04a5one.dts | 21 /* data lines, gpmc_d0..d7 not muxable according to TRM */
32 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
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| H A D | omap3-n900.dts | 244 /* data lines, gpmc_d0..d7 not muxable according to TRM */
255 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
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| /linux/drivers/pinctrl/mvebu/ |
| H A D | pinctrl-mvebu.h | 38 * A mpp_ctrl describes a muxable unit, e.g. pin, group of pins, or
39 * internal function, inside the SoC. Each muxable unit can be switched
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| /linux/Documentation/devicetree/bindings/display/imx/ |
| H A D | fsl,imx6qp-prg.yaml | 33 PRE as the first entry and the muxable PREs following.
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| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | cirrus,cs48l32.yaml | 76 independently configured, as are the two groups of pins muxable to
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| /linux/drivers/pinctrl/bcm/ |
| H A D | pinctrl-nsp-mux.c | 143 * List of muxable pins in nsp
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| /linux/arch/arm/boot/dts/qcom/ |
| H A D | qcom-apq8060-dragonboard.dts | 857 * The SDCC3 pins are hardcoded (non-muxable) but need some pin
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| /linux/drivers/pinctrl/ |
| H A D | pinctrl-artpec6.c | 27 #define ARTPEC6_MAX_MUXABLE 35 /* Last pin with muxable function */
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| /linux/drivers/pinctrl/sunplus/ |
| H A D | sppctl_sp7021.c | 66 /* gpio, iop, muxable */
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