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/linux/Documentation/devicetree/bindings/
H A Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
32 - enum:
34 - acbel,fsg032
35 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
36 - ad,ad7414 # Deprecated, use adi,ad7414
[all …]
/linux/drivers/eisa/
H A Deisa.ids6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
25 ACE7010 "ACME Multi-Function Board"
39 ACR1711 "AcerFrame 1000 486/33 SYSTEM-2"
41 ACR3211 "AcerFrame 3000MP 486 SYSTEM-1"
[all …]
/linux/drivers/media/dvb-frontends/drx39xyj/
H A Ddrx_dap_fasi.h2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
48 /*-------- compilation control switches --------------------------------------*/
53 /*-------- Required includes -------------------------------------------------*/
57 /*-------- Defines, configuring the API --------------------------------------*/
98 #error At least one of short- or long-addressing format must be allowed.
103 * Single/master multi master setting
106 * Comments about SINGLE MASTER/MULTI MASTER modes:
113 * + multi master mode means use of repeated starts
118 * Single/multi master selected via the flags in the FASI protocol.
121 * Default is single master, DAP FASI changes multi-master setting silently
[all …]
/linux/arch/parisc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T if !64BIT
20 select ARCH_SPLIT_ARG64 if !64BIT
40 select GENERIC_ATOMIC64 if !64BIT
83 select HAVE_DYNAMIC_FTRACE if $(cc-option,-fpatchable-function-entry=1,1)
90 select HAVE_FUNCTION_DESCRIPTORS if 64BIT
94 The PA-RISC microprocessor is designed by Hewlett-Packard and used
96 and later HP3000 series). The PA-RISC Linux project home page is
124 select GENERIC_BUG_RELATIVE_POINTERS if 64BIT
143 default 18 if 64BIT
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/linux/Documentation/devicetree/bindings/display/
H A Dmulti-inno,mi0283qt.txt1 Multi-Inno MI0283QT display panel
4 - compatible: "multi-inno,mi0283qt".
7 all mandatory properties described in ../spi/spi-bus.txt must be specified.
10 - dc-gpios: D/C pin. The presence/absence of this GPIO determines
12 - present: IM=x110 4-wire 8-bit data serial interface
13 - absent: IM=x101 3-wire 9-bit data serial interface
14 - reset-gpios: Reset pin
15 - power-supply: A regulator node for the supply voltage.
16 - backlight: phandle of the backlight device attached to the panel
17 - rotation: panel rotation in degrees counter clockwise (0,90,180,270)
[all …]
/linux/arch/riscv/kernel/
H A Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <asm/text-patching.h>
30 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
39 /* Per-cpu ISA extensions. */
43 * riscv_isa_extension_base() - Get base extension word
59 * __riscv_isa_extension_available() - Check whether given extension
63 * @bit: bit position of the desired extension
68 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit) in __riscv_isa_extension_available() argument
72 if (bit >= RISCV_ISA_EXT_MAX) in __riscv_isa_extension_available()
75 return test_bit(bit, bmap) ? true : false; in __riscv_isa_extension_available()
[all …]
/linux/arch/powerpc/kvm/
H A Dbook3s_hv_ras.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #define SRR1_MC_LDSTERR (1ul << (63-42))
22 #define SRR1_MC_IFETCH_SH (63-45)
25 #define SRR1_MC_IFETCH_SLBMULTI 3 /* SLB multi-hit */
26 #define SRR1_MC_IFETCH_SLBPARMULTI 4 /* SLB parity + multi-hit */
27 #define SRR1_MC_IFETCH_TLBMULTI 5 /* I-TLB multi-hit */
30 #define DSISR_MC_DERAT_MULTI 0x800 /* D-ERAT multi-hit */
31 #define DSISR_MC_TLB_MULTI 0x400 /* D-TLB multi-hit */
33 #define DSISR_MC_SLB_MULTI 0x080 /* SLB multi-hit */
34 #define DSISR_MC_SLB_PARMULTI 0x040 /* SLB parity + multi-hit */
[all …]
/linux/sound/pci/ctxfi/
H A Dctresource.c1 // SPDX-License-Identifier: GPL-2.0-only
21 /* Resource allocation based on bit-map management mechanism */
24 unsigned int multi, unsigned int *ridx) in get_resource() argument
29 for (i = 0, n = multi; i < amount; i++) { in get_resource()
33 n = multi; in get_resource()
36 if (!(--n)) in get_resource()
42 return -ENOENT; in get_resource()
45 /* Mark the contiguous bits in resource bit-map as used */ in get_resource()
46 for (n = multi; n > 0; n--) { in get_resource()
50 i--; in get_resource()
[all …]
/linux/arch/sh/mm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
12 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
15 On other systems (such as the SH-3 and 4) where an MMU exists,
26 On MMU-less systems, any of these page sizes can be selected
80 config 29BIT
81 def_bool !32BIT
84 config 32BIT
89 bool "Support 32-bit physical addressing through PMB"
91 select 32BIT
95 32-bits through the SH-4A PMB. If this is not set, legacy
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dmac.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022, 2024 Intel Corporation
11 * AUX indices follows - 1 for non-CDB, 2 for CDB.
31 * enum iwl_mac_protection_flags - MAC context flags
40 MAC_PROT_FLG_TGG_PROTECT = BIT(3),
41 MAC_PROT_FLG_HT_PROT = BIT(23),
42 MAC_PROT_FLG_FAT_PROT = BIT(24),
43 MAC_PROT_FLG_SELF_CTS_EN = BIT(30),
46 #define MAC_FLG_SHORT_SLOT BIT(4)
47 #define MAC_FLG_SHORT_PREAMBLE BIT(5)
[all …]
/linux/sound/soc/sof/
H A Dipc4-topology.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
14 #define SOF_IPC4_FW_PAGE_SIZE BIT(12)
15 #define SOF_IPC4_FW_PAGE(x) ((((x) + BIT(12) - 1) & ~(BIT(1
[all...]
/linux/drivers/gpu/drm/xe/
H A Dxe_tile.c1 // SPDX-License-Identifier: MIT
6 #include <linux/fault-inject.h>
22 * DOC: Multi-tile Design
24 * Different vendors use the term "tile" a bit differently, but in the Intel
27 * that's what is referred to as a "multi-tile device." In such cases, pretty
28 * much all hardware is replicated per-tile, although certain responsibilities
30 * solely by the "root tile." A multi-tile platform takes care of tying the
32 * are forwarded to the root tile, the per-tile vram is combined into a single
41 * Historically most Intel devices were single-tile devices that contained a
42 * single GT. PVC is an example of an Intel platform built on a multi-tile
[all …]
H A Dxe_exec_queue_types.h1 /* SPDX-License-Identifier: MIT */
25 XE_EXEC_QUEUE_PRIORITY_UNSET = -2, /* For execlist usage only */
35 * struct xe_exec_queue - Execution queue
70 * @last_fence: last fence on exec queue, protected by vm->lock in write
71 * mode if bind exec queue, protected by dma resv lock if non-bind exec
77 #define EXEC_QUEUE_FLAG_KERNEL BIT(0)
79 #define EXEC_QUEUE_FLAG_PERMANENT BIT(1)
81 #define EXEC_QUEUE_FLAG_VM BIT(2)
82 /* child of VM queue for multi-tile VM jobs */
83 #define EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD BIT(3)
[all …]
/linux/Documentation/admin-guide/mm/
H A Dmultigen_lru.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Multi-Gen LRU
6 The multi-gen LRU is an alternative LRU implementation that optimizes
26 -----------
38 0x0001 The main switch for the multi-gen LRU.
39 0x0002 Clearing the accessed bit in leaf page table entries in large
42 disabled, the multi-gen LRU will suffer a minor performance
46 0x0004 Clearing the accessed bit in non-leaf page table entries as
49 disabled, the multi-gen LRU will suffer a negligible
65 --------------------
[all …]
/linux/include/linux/soundwire/
H A Dsdw_intel.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
26 #define SDW_SHIM_LCAP_MLCS_MASK BIT(8)
31 #define SDW_SHIM_LCTL_SPA BIT(0)
33 #define SDW_SHIM_LCTL_CPA BIT(8)
43 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
44 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24_576 (24576 / SDW_CADENCE_GSYNC_KHZ - 1)
45 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
46 #define SDW_SHIM_SYNC_SYNCPRD_VAL_96 (96000 / SDW_CADENCE_GSYNC_KHZ - 1)
48 #define SDW_SHIM_SYNC_SYNCCPU BIT(15)
[all …]
/linux/drivers/zorro/
H A Dzorro.ids4 # Maintained by Geert Uytterhoeven <zorro@linux-m68k.org>
12 # product product_name <-- single tab
23 0200 3-State
29 6700 A2386-SX [ISA Bus Bridge]
38 4500 A2232 Prototype [Multi I/O]
39 4600 A2232 [Multi I/O]
46 6700 A2386-SX [ISA Bus Bridge]
61 03ed A-Squared
70 0300 8-Up (Rev A) [RAM Expansion]
71 0400 8-Up (Rev Z) [RAM Expansion]
[all …]
/linux/Documentation/input/devices/
H A Dsentelic.rst8 :Copyright: |copy| 2002-2011 Sentelic Corporation.
10 :Last update: Dec-07-2011
27 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
28 BYTE |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
30 |---------------| |---------------| |---------------| |---------------|
34 Bit5 => Y sign bit
35 Bit4 => X sign bit
40 Byte 2: X Movement(9-bit 2's complement integers)
41 Byte 3: Y Movement(9-bit 2's complement integers)
43 valid values, -8 ~ +7
[all …]
/linux/Documentation/sound/cards/
H A Dcmipci.rst2 Brief Notes on C-Media 8338/8738/8768/8770 Driver
8 Front/Rear Multi-channel Playback
9 ---------------------------------
13 DACs, both streams are handled independently unlike the 4/6ch multi-
22 - The first DAC supports U8 and S16LE formats, while the second DAC
24 - The second DAC supports only two channel stereo.
43 front one) and was so excited. It was even with "Four Channel" bit
51 control switch in the driver "Line-In As Rear", which you can change
52 via alsamixer or somewhat else. When this switch is on, line-in jack
60 4/6 Multi-Channel Playback
[all …]
/linux/drivers/pwm/
H A Dpwm-bcm-iproc.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #define IPROC_PWM_PRESCALE_SHIFT(ch) ((3 - (ch)) * \
50 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_enable()
52 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_enable()
54 /* must be a 400 ns delay between clearing and setting enable bit */ in iproc_pwmc_enable()
62 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_disable()
64 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_disable()
66 /* must be a 400 ns delay between clearing and setting enable bit */ in iproc_pwmc_disable()
74 u64 tmp, multi, rate; in iproc_pwmc_get_state() local
77 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_get_state()
[all …]
/linux/drivers/ata/
H A Dpata_ftide010.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * struct ftide010 - state container for the Faraday FTIDE010
48 /* Gemini-specific properties */
76 /* Set this bit for UDMA mode 5 and 6 */
77 #define FTIDE010_UDMA_TIMING_MODE_56 BIT(7)
80 #define FTIDE010_CLK_MOD_DEV0_CLK_SEL BIT(0)
81 #define FTIDE010_CLK_MOD_DEV1_CLK_SEL BIT(1)
83 #define FTIDE010_CLK_MOD_DEV0_UDMA_EN BIT(4)
84 #define FTIDE010_CLK_MOD_DEV1_UDMA_EN BIT(5)
102 * mdma_50_active_time: array of 4 elements for Td timing for multi
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A Dfloating-point.json5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
20 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.",
27 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.",
34 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
[all …]
/linux/arch/sparc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 config 64BIT
3 bool "64-bit kernel" if "$(ARCH)" = "sparc"
10 Say yes to build a 64-bit kernel - formerly known as sparc64
11 Say no to build a 32-bit kernel - formerly known as sparc
54 def_bool !64BIT
70 def_bool 64BIT
145 default 4 if 64BIT
154 bool "Symmetric multi-processing support"
160 If you say N here, the kernel will run on uni- and multiprocessor
[all …]
/linux/Documentation/devicetree/bindings/leds/
H A Dallwinner,sun50i-a100-ledc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/leds/allwinner,sun50i-a100-ledc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Samuel Holland <samuel@sholland.org>
13 The LED controller found in Allwinner sunxi SoCs uses a one-wire serial
19 - const: allwinner,sun50i-a100-ledc
20 - items:
21 - enum:
22 - allwinner,sun20i-d1-ledc
[all …]
/linux/drivers/iio/dac/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
22 module will be called ad3552r-hs.
41 tristate "Analog Devices AD5064 and similar multi-channel DAC driver"
45 AD5045, AD5064, AD5064-1, AD5065, AD5625, AD5625R, AD5627, AD5627R,
59 AD5362, AD5363, AD5370, AD5371, AD5373 multi-channel
72 AD5382, AD5383, AD5384, AD5390, AD5391, AD5392 multi-channel
82 Say yes here to build support for Analog Devices AD5421 loop-powered
83 digital-to-analog convertors (DAC).
161 Say yes here to build support for Analog Devices AD9739A Digital-to
181 digital-to-analog (DAC) converters that require either a high-speed
[all …]
/linux/Documentation/devicetree/bindings/arm/
H A Dqcom,coresight-tpdm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/qcom,coresight-tpdm.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Trace, Profiling and Diagnostics Monitor - TPDM
13 Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete
14 Single Bit (DSB). It performs data collection in the data producing clock
22 - Mao Jinlong <quic_jinlmao@quicinc.com>
23 - Tao Zhang <quic_taozha@quicinc.com>
31 - qcom,coresight-tpdm
[all …]

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