| /linux/drivers/pci/controller/ |
| H A D | pcie-iproc-msi.c | 9 #include <linux/msi.h>
34 /* Size of each MSI address region */
52 * struct iproc_msi_grp - iProc MSI group
54 * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
57 * @msi: pointer to iProc MSI data
62 struct iproc_msi *msi; member
68 * struct iproc_msi - iProc event queue based MSI
70 * Only meant to be used on platforms without MSI support integrated into the
74 * @reg_offsets: MSI register offsets
75 * @grps: MSI groups
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| H A D | pci-xgene-msi.c | 3 * APM X-Gene MSI Driver
13 #include <linux/msi.h>
27 struct xgene_msi *msi; member
48 .name = "X-Gene1 MSI",
62 * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where
85 * Each index register supports 16 MSI vectors (0..15) to generate interrupt.
86 * There are total 16 GIC IRQs assigned for these 16 groups of MSI termination
89 * Each MSI termination group has 1 MSIINTn register (n is 0..15) to indicate
90 * the MSI pending status caused by 1 of its 8 index registers.
94 static u32 xgene_msi_ir_read(struct xgene_msi *msi, in xgene_msi_ir_read() argument
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | pci-msi.txt | 2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
38 * msi-controller is a single phandle to an MSI controller
40 * msi-base is an msi-specifier describing the msi-specifier produced for the
47 the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
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| H A D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
16 Each PCIe node needs to have property msi-parent that points to an MSI
23 + MSI node:
24 msi@79000000 {
25 compatible = "apm,xgene1-msi";
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | msi.txt | 1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
17 they can address. An MSI controller may feature a number of doorbells.
22 MSI controllers may have restrictions on permitted payloads.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
35 address by some master. An MSI controller may feature a number of doorbells.
40 - msi-controller: Identifies the node as an MSI controller.
45 - #msi-cells: The number of cells in an msi-specifier, required if not zero.
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| H A D | fsl,ls-msi.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
7 title: Freescale Layerscape SCFG PCIe MSI controller
15 Each PCIe node needs to have property msi-parent that points to
16 MSI controller node
24 - fsl,ls1012a-msi
25 - fsl,ls1021a-msi
26 - fsl,ls1043a-msi
27 - fsl,ls1043a-v1.1-msi
28 - fsl,ls1046a-msi
33 '#msi-cells':
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| H A D | loongson,pch-msi.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
7 title: Loongson PCH MSI Controller
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
27 to PCH MSI.
32 loongson,msi-num-vecs:
35 to PCH MSI.
40 msi-controller: true
45 - msi-controller
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| H A D | fsl,mu-msi.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
7 title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
25 MU can work as msi interrupt controller to do doorbell
28 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
33 - fsl,imx6sx-mu-msi
34 - fsl,imx7ulp-mu-msi
35 - fsl,imx8ulp-mu-msi
36 - fsl,imx8ulp-mu-msi-s4
67 msi-controller: true
69 "#msi-cells":
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| H A D | msi-controller.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
7 title: MSI controller
13 An MSI controller signals interrupts to a CPU when a write is made
14 to an MMIO address by some master. An MSI controller may feature a
18 "#msi-cells":
20 The number of cells in an msi-specifier, required if not zero.
26 The meaning of the msi-specifier is defined by the device tree
27 binding of the specific MSI controller.
30 msi-controller:
32 Identifies the node as an MSI controller.
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| H A D | al,alpine-msix.txt | 3 See arm,gic-v3.txt for SPI and MSI definitions.
10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
22 msi-controller;
23 al,msi-base-spi = <160>;
24 al,msi-num-spis = <160>;
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| H A D | riscv,imsics.yaml | 7 title: RISC-V Incoming MSI Controller (IMSIC)
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
32 RISC-V platform. The MSI target address of a IMSIC interrupt file at given
44 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
64 msi-controller: true
66 "#msi-cells":
99 Number of guest index bits in the MSI target address.
105 Number of HART index bits in the MSI target address. When not
113 Number of group index bits in the MSI target address.
122 MSI target address.
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| /linux/arch/arm64/kvm/vgic/ |
| H A D | vgic-irqfd.c | 55 e->msi.address_lo = ue->u.msi.address_lo; in kvm_set_routing_entry()
56 e->msi.address_hi = ue->u.msi.address_hi; in kvm_set_routing_entry()
57 e->msi.data = ue->u.msi.data; in kvm_set_routing_entry()
58 e->msi.flags = ue->flags; in kvm_set_routing_entry()
59 e->msi.devid = ue->u.msi.devid; in kvm_set_routing_entry()
70 struct kvm_msi *msi) in kvm_populate_msi() argument
72 msi->address_lo = e->msi.address_lo; in kvm_populate_msi()
73 msi->address_hi = e->msi.address_hi; in kvm_populate_msi()
74 msi->data = e->msi.data; in kvm_populate_msi()
75 msi->flags = e->msi.flags; in kvm_populate_msi()
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | msi-pic.txt | 1 * Freescale MSI interrupt controller
5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
17 region must be added because different MSI group has different MSIIR1 offset.
21 be set as edge sensitive. If msi-available-ranges is present, only
25 - msi-available-ranges: use <start count> style section to define which
26 msi interrupt can be used in the 256 msi interrupts. This property is
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| /linux/drivers/pci/msi/ |
| H A D | irqdomain.c | 3 * PCI Message Signaled Interrupt (MSI) - irqdomain support
9 #include "msi.h"
36 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
37 * @irq_data: Pointer to interrupt data of the MSI interrupt
45 * For MSI-X desc->irq is always equal to irq_data->irq. For in pci_msi_domain_write_msg()
46 * MSI only the first interrupt of MULTI MSI passes the test. in pci_msi_domain_write_msg()
53 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
54 * @desc: Pointer to the MSI descriptor
104 * pci_msi_create_irq_domain - Create a MSI interrupt domain
106 * @info: MSI domain info
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| H A D | msi.c | 3 * PCI Message Signaled Interrupt (MSI)
15 #include "msi.h"
21 * pci_msi_supported - check whether MSI may be enabled on a device
22 * @dev: pointer to the pci_dev data structure of MSI device function
26 * to determine if MSI/-X are supported for the device. If MSI/-X is
33 /* MSI must be globally enabled and supported by the device */ in pci_msi_supported()
49 * Any bridge which does NOT route MSI transactions from its in pci_msi_supported()
59 * the NO_MSI flag when no MSI domain is found for this bridge in pci_msi_supported()
79 * vs. msi_device_data_release() in the MSI core code.
97 * Ordering vs. devres: msi device data has to be installed first so that
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| /linux/kernel/irq/ |
| H A D | msi.c | 14 #include <linux/msi.h>
25 * struct msi_device_data - MSI per device data
26 * @properties: MSI properties which are interesting to drivers
27 * @mutex: Mutex protecting the MSI descriptor store
28 * @__domains: Internal data for per device MSI domains
39 * struct msi_ctrl - MSI internal management control structure
44 * than the range due to PCI/multi-MSI.
103 struct msi_device_data *md = dev->msi.data; in msi_insert_desc()
139 * msi_domain_insert_msi_desc - Allocate and initialize a MSI descriptor and
144 * @init_desc: Pointer to an MSI descripto
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| /linux/arch/mips/pci/ |
| H A D | msi-octeon.c | 10 #include <linux/msi.h>
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
31 * is used so we can disable all of the MSI interrupts when a device
43 * Number of MSI IRQs used. This variable is set up in
49 * arch_setup_msi_irq() - setup MSI IRQs for a device
50 * @dev: Device requesting MSI interrupts
51 * @desc: MSI descriptor
53 * Called when a driver requests MSI interrupts instead of the
55 * for MSI devices that support them. A device can override this by
56 * programming the MSI control bits [6:4] before calling
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| /linux/drivers/ntb/ |
| H A D | msi.c | 6 #include <linux/msi.h>
19 * ntb_msi_init() - Initialize the MSI context
23 * It initializes the context for MSI operations and maps
45 ntb->msi = devm_kzalloc(&ntb->dev, struct_size(ntb->msi, peer_mws, peers), in ntb_msi_init()
47 if (!ntb->msi) in ntb_msi_init()
50 ntb->msi->desc_changed = desc_changed; in ntb_msi_init()
60 ntb->msi->peer_mws[i] = devm_ioremap(&ntb->dev, mw_phys_addr, in ntb_msi_init()
62 if (!ntb->msi->peer_mws[i]) { in ntb_msi_init()
72 if (ntb->msi->peer_mws[i]) in ntb_msi_init()
73 devm_iounmap(&ntb->dev, ntb->msi->peer_mws[i]); in ntb_msi_init()
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| /linux/arch/riscv/kvm/ |
| H A D | vm.c | 71 struct kvm_msi msi; in kvm_set_msi() local
76 msi.address_lo = e->msi.address_lo; in kvm_set_msi()
77 msi.address_hi = e->msi.address_hi; in kvm_set_msi()
78 msi.data = e->msi.data; in kvm_set_msi()
79 msi.flags = e->msi.flags; in kvm_set_msi()
80 msi.devid = e->msi.devid; in kvm_set_msi()
82 return kvm_riscv_aia_inject_msi(kvm, &msi); in kvm_set_msi()
135 e->msi.address_lo = ue->u.msi.address_lo; in kvm_set_routing_entry()
136 e->msi.address_hi = ue->u.msi.address_hi; in kvm_set_routing_entry()
137 e->msi.data = ue->u.msi.data; in kvm_set_routing_entry()
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| /linux/Documentation/PCI/endpoint/ |
| H A D | pci-test-howto.rst | 79 to change the vendorid and the number of MSI interrupts used by the function
158 SET IRQ TYPE TO MSI: OKAY
191 SET IRQ TYPE TO MSI-X: OKAY
192 MSI-X1: OKAY
193 MSI-X2: OKAY
194 MSI-X3: OKAY
195 MSI-X4: OKAY
196 MSI-X5: OKAY
197 MSI-X6: OKAY
198 MSI-X7: OKAY
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| /linux/drivers/irqchip/ |
| H A D | irq-msi-lib.c | 7 #include "irq-msi-lib.h"
10 * msi_lib_init_dev_msi_info - Domain info setup for MSI domains
18 * This function is to be used for all types of MSI domains above the root
38 * MSI parent domain specific settings. For now there is only the in msi_lib_init_dev_msi_info()
39 * root parent domain, e.g. NEXUS, acting as a MSI parent, but it is in msi_lib_init_dev_msi_info()
40 * possible to stack MSI parents. See x86 vector -> irq remapping in msi_lib_init_dev_msi_info()
62 * Per device MSI should never have any MSI feature bits in msi_lib_init_dev_msi_info()
70 /* Core managed MSI descriptors */ in msi_lib_init_dev_msi_info()
87 * Mask out the domain specific MSI feature flags which are not in msi_lib_init_dev_msi_info()
101 * The device MSI domain can never have a set affinity callback. It in msi_lib_init_dev_msi_info()
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| /linux/drivers/virt/acrn/ |
| H A D | vm.c | 97 * acrn_msi_inject() - Inject a MSI interrupt into a User VM
99 * @msi_addr: The MSI address
100 * @msi_data: The MSI data
106 struct acrn_msi_entry *msi; in acrn_msi_inject() local
110 msi = kzalloc(sizeof(*msi), GFP_ATOMIC); in acrn_msi_inject()
111 if (!msi) in acrn_msi_inject()
118 msi->msi_addr = msi_addr; in acrn_msi_inject()
119 msi->msi_data = msi_data; in acrn_msi_inject()
120 ret = hcall_inject_msi(vm->vmid, virt_to_phys(msi)); in acrn_msi_inject()
123 "Failed to inject MSI to VM %u!\n", vm->vmid); in acrn_msi_inject()
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| /linux/Documentation/devicetree/bindings/misc/ |
| H A D | fsl,qoriq-mc.yaml | 41 The MSI writes are accompanied by sideband data which is derived from the ICID.
42 The msi-map property is used to associate the devices with both the ITS
45 For generic MSI bindings, see
46 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
102 msi-map:
104 Maps an ICID to a GIC ITS and associated msi-specifier
108 (icid-base,gic-its,msi-base,length).
111 associated with the listed GIC ITS, with the msi-specifier
112 (i - icid-base + msi-base).
114 msi-parent:
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| /linux/arch/s390/pci/ |
| H A D | pci_irq.c | 9 #include <linux/msi.h>
147 .name = "PCI-MSI",
303 struct msi_desc *msi; in arch_setup_msi_irqs() local
323 * Request MSI interrupts: in arch_setup_msi_irqs()
324 * When using MSI, nvec_used interrupt sources and their irq in arch_setup_msi_irqs()
325 * descriptors are controlled through one msi descriptor. in arch_setup_msi_irqs()
326 * Thus the outer loop over msi descriptors shall run only once, in arch_setup_msi_irqs()
328 * When using MSI-X, each interrupt vector/irq descriptor in arch_setup_msi_irqs()
329 * is bound to exactly one msi descriptor (nvec_used is one). in arch_setup_msi_irqs()
331 * over the MSI-X descriptors. in arch_setup_msi_irqs()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/pci/ |
| H A D | base.c | 35 if (pci && pci->msi) in nvkm_pci_msi_rearm()
128 /* Ensure MSI interrupts are armed, for the case where there are in nvkm_pci_init()
131 if (pci->msi) in nvkm_pci_init()
144 if (pci->msi) in nvkm_pci_dtor()
187 pci->msi = true; in nvkm_pci_new_()
193 pci->msi = false; in nvkm_pci_new_()
196 pci->msi = nvkm_boolopt(device->cfgopt, "NvMSI", pci->msi); in nvkm_pci_new_()
197 if (pci->msi && func->msi_rearm) { in nvkm_pci_new_()
198 pci->msi = pci_enable_msi(pci->pdev) == 0; in nvkm_pci_new_()
199 if (pci->msi) in nvkm_pci_new_()
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