Searched +full:mpfs +full:- +full:mss +full:- +full:top +full:- +full:sysreg (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg register region10 - Conor Dooley <conor.dooley@microchip.com>13 An wide assortment of registers that control elements of the MSS on PolarFire19 - const: microchip,mpfs-mss-top-sysreg20 - const: syscon21 - const: simple-mfd[all …]
1 // SPDX-License-Identifier: GPL-2.011 MFD_CELL_NAME("mpfs-reset"),16 struct device *dev = &pdev->dev; in mpfs_mss_top_sysreg_probe()28 { .compatible = "microchip,mpfs-mss-top-sysreg", },35 .name = "mpfs-mss-top-sysreg",44 MODULE_DESCRIPTION("PolarFire SoC mss top sysreg driver");
1 obj-$(CONFIG_POLARFIRE_SOC_SYS_CTRL) += mpfs-sys-controller.o2 obj-$(CONFIG_POLARFIRE_SOC_SYSCONS) += mpfs-control-scb.o mpfs-mss-top-sysreg.o
1 // SPDX-License-Identifier: GPL-2.0-only3 * PolarFire SoC MSS/core complex clock control5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.8 #include <linux/clk-provider.h>14 #include <dt-bindings/clock/microchip,mpfs-clock.h>15 #include <soc/microchip/mpfs.h>144 * MSS PLL internal clock150 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_recalc_rate()151 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_recalc_rate()189 msspll_hw->base = data->msspll_base; in mpfs_clk_register_mssplls()[all …]