Home
last modified time | relevance | path

Searched full:mmhub (Results 1 – 25 of 35) sorted by relevance

12

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v1_0.c27 #include "mmhub/mmhub_1_0_offset.h"
28 #include "mmhub/mmhub_1_0_sh_mask.h"
29 #include "mmhub/mmhub_1_0_default.h"
39 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); in mmhub_v1_0_get_fb_location()
40 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP); in mmhub_v1_0_get_fb_location()
59 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v1_0_setup_vm_pt_regs()
63 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v1_0_setup_vm_pt_regs()
74 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v1_0_init_gart_aperture_regs()
76 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v1_0_init_gart_aperture_regs()
79 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v1_0_init_gart_aperture_regs()
[all …]
H A Dmmhub_v2_3.c27 #include "mmhub/mmhub_2_3_0_offset.h"
28 #include "mmhub/mmhub_2_3_0_sh_mask.h"
29 #include "mmhub/mmhub_2_3_0_default.h"
126 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v2_3_setup_vm_pt_regs()
129 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v2_3_setup_vm_pt_regs()
139 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v2_3_init_gart_aperture_regs()
141 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v2_3_init_gart_aperture_regs()
144 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v2_3_init_gart_aperture_regs()
146 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v2_3_init_gart_aperture_regs()
156 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); in mmhub_v2_3_init_system_aperture_regs()
[all …]
H A Dmmhub_v4_1_0.c27 #include "mmhub/mmhub_4_1_0_offset.h"
28 #include "mmhub/mmhub_4_1_0_sh_mask.h"
75 /* Only use legacy inv on mmhub side */ in mmhub_v4_1_0_get_invalidate_req()
133 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v4_1_0_setup_vm_pt_regs()
137 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v4_1_0_setup_vm_pt_regs()
148 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v4_1_0_init_gart_aperture_regs()
150 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v4_1_0_init_gart_aperture_regs()
153 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v4_1_0_init_gart_aperture_regs()
155 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v4_1_0_init_gart_aperture_regs()
173 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); in mmhub_v4_1_0_init_system_aperture_regs()
[all …]
H A Dmmhub_v3_0.c27 #include "mmhub/mmhub_3_0_0_offset.h"
28 #include "mmhub/mmhub_3_0_0_sh_mask.h"
141 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v3_0_setup_vm_pt_regs()
145 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v3_0_setup_vm_pt_regs()
156 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v3_0_init_gart_aperture_regs()
158 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v3_0_init_gart_aperture_regs()
161 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v3_0_init_gart_aperture_regs()
163 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v3_0_init_gart_aperture_regs()
181 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); in mmhub_v3_0_init_system_aperture_regs()
182 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_init_system_aperture_regs()
[all …]
H A Dmmhub_v3_0_1.c27 #include "mmhub/mmhub_3_0_1_offset.h"
28 #include "mmhub/mmhub_3_0_1_sh_mask.h"
150 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v3_0_1_setup_vm_pt_regs()
154 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v3_0_1_setup_vm_pt_regs()
165 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v3_0_1_init_gart_aperture_regs()
167 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v3_0_1_init_gart_aperture_regs()
170 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v3_0_1_init_gart_aperture_regs()
172 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v3_0_1_init_gart_aperture_regs()
182 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); in mmhub_v3_0_1_init_system_aperture_regs()
183 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_1_init_system_aperture_regs()
[all …]
H A Dmmhub_v2_0.c27 #include "mmhub/mmhub_2_0_0_offset.h"
28 #include "mmhub/mmhub_2_0_0_sh_mask.h"
29 #include "mmhub/mmhub_2_0_0_default.h"
192 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v2_0_setup_vm_pt_regs()
196 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v2_0_setup_vm_pt_regs()
207 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
209 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
212 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
214 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
225 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); in mmhub_v2_0_init_system_aperture_regs()
[all …]
H A Dmmhub_v3_3.c27 #include "mmhub/mmhub_3_3_0_offset.h"
28 #include "mmhub/mmhub_3_3_0_sh_mask.h"
242 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v3_3_setup_vm_pt_regs()
246 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v3_3_setup_vm_pt_regs()
258 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v3_3_init_gart_aperture_regs()
260 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v3_3_init_gart_aperture_regs()
263 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v3_3_init_gart_aperture_regs()
265 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v3_3_init_gart_aperture_regs()
275 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); in mmhub_v3_3_init_system_aperture_regs()
276 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_3_init_system_aperture_regs()
[all …]
H A Dmmhub_v3_0_2.c27 #include "mmhub/mmhub_3_0_2_offset.h"
28 #include "mmhub/mmhub_3_0_2_sh_mask.h"
134 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v3_0_2_setup_vm_pt_regs()
138 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v3_0_2_setup_vm_pt_regs()
149 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v3_0_2_init_gart_aperture_regs()
151 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v3_0_2_init_gart_aperture_regs()
154 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v3_0_2_init_gart_aperture_regs()
156 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v3_0_2_init_gart_aperture_regs()
166 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); in mmhub_v3_0_2_init_system_aperture_regs()
167 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_2_init_system_aperture_regs()
[all …]
H A Damdgpu_mmhub.c29 if (!adev->mmhub.ras) in amdgpu_mmhub_ras_sw_init()
32 ras = adev->mmhub.ras; in amdgpu_mmhub_ras_sw_init()
35 dev_err(adev->dev, "Failed to register mmhub ras block!\n"); in amdgpu_mmhub_ras_sw_init()
39 strcpy(ras->ras_block.ras_comm.name, "mmhub"); in amdgpu_mmhub_ras_sw_init()
42 adev->mmhub.ras_if = &ras->ras_block.ras_comm; in amdgpu_mmhub_ras_sw_init()
44 /* mmhub ras follows amdgpu_ras_block_late_init_default for late init */ in amdgpu_mmhub_ras_sw_init()
H A Dimu_v12_0.c33 #include "mmhub/mmhub_4_1_0_offset.h"
309 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in imu_v12_init_gfxhub_settings()
311 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_TOP); in imu_v12_init_gfxhub_settings()
313 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET); in imu_v12_init_gfxhub_settings()
315 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE); in imu_v12_init_gfxhub_settings()
317 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT); in imu_v12_init_gfxhub_settings()
319 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP); in imu_v12_init_gfxhub_settings()
321 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in imu_v12_init_gfxhub_settings()
323 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR); in imu_v12_init_gfxhub_settings()
325 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR); in imu_v12_init_gfxhub_settings()
[all …]
H A Dgmc_v11_0.c162 entry->vmid_src ? "mmhub" : "gfxhub", in gmc_v11_0_process_interrupt()
311 /* Issue additional private vm invalidation to MMHUB */ in gmc_v11_0_flush_gpu_tlb()
596 adev->mmhub.funcs = &mmhub_v3_0_1_funcs; in gmc_v11_0_set_mmhub_funcs()
599 adev->mmhub.funcs = &mmhub_v3_0_2_funcs; in gmc_v11_0_set_mmhub_funcs()
604 adev->mmhub.funcs = &mmhub_v3_3_funcs; in gmc_v11_0_set_mmhub_funcs()
607 adev->mmhub.funcs = &mmhub_v3_0_funcs; in gmc_v11_0_set_mmhub_funcs()
672 base = adev->mmhub.funcs->get_fb_location(adev); in gmc_v11_0_vram_gtt_location()
686 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); in gmc_v11_0_vram_gtt_location()
717 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); in gmc_v11_0_mc_init()
763 adev->mmhub.funcs->init(adev); in gmc_v11_0_sw_init()
[all …]
H A Dgmc_v9_0.c38 #include "mmhub/mmhub_1_0_offset.h"
333 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
334 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
495 tmp = RREG32_SOC15_IP(MMHUB, reg); in gmc_v9_0_vm_fault_interrupt_state()
502 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
523 tmp = RREG32_SOC15_IP(MMHUB, reg); in gmc_v9_0_vm_fault_interrupt_state()
530 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
884 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
897 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
912 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
[all …]
H A Dgmc_v12_0.c155 entry->vmid_src ? "mmhub" : "gfxhub", in gmc_v12_0_process_interrupt()
288 /* Issue additional private vm invalidation to MMHUB */ in gmc_v12_0_flush_vm_hub()
375 /* Only need to invalidate mm_hub now, gfx12 only support one mmhub */ in gmc_v12_0_flush_gpu_tlb_pasid()
624 adev->mmhub.funcs = &mmhub_v4_1_0_funcs; in gmc_v12_0_set_mmhub_funcs()
684 base = adev->mmhub.funcs->get_fb_location(adev); in gmc_v12_0_vram_gtt_location()
696 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); in gmc_v12_0_vram_gtt_location()
728 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); in gmc_v12_0_mc_init()
775 adev->mmhub.funcs->init(adev); in gmc_v12_0_sw_init()
917 r = adev->mmhub.funcs->gart_enable(adev); in gmc_v12_0_gart_enable()
926 adev->mmhub.funcs->set_fault_enable_default(adev, value); in gmc_v12_0_gart_enable()
[all …]
H A Dgmc_v10_0.c165 entry->vmid_src ? "mmhub" : "gfxhub", in gmc_v10_0_process_interrupt()
602 adev->mmhub.funcs = &mmhub_v2_3_funcs; in gmc_v10_0_set_mmhub_funcs()
605 adev->mmhub.funcs = &mmhub_v2_0_funcs; in gmc_v10_0_set_mmhub_funcs()
776 adev->mmhub.funcs->init(adev); in gmc_v10_0_sw_init()
959 r = adev->mmhub.funcs->gart_enable(adev); in gmc_v10_0_gart_enable()
972 adev->mmhub.funcs->set_fault_enable_default(adev, value); in gmc_v10_0_gart_enable()
1028 adev->mmhub.funcs->gart_disable(adev); in gmc_v10_0_gart_disable()
1091 * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled in gmc_v10_0_set_clockgating_state()
1097 dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n"); in gmc_v10_0_set_clockgating_state()
1101 r = adev->mmhub.funcs->set_clockgating(adev, state); in gmc_v10_0_set_clockgating_state()
[all …]
H A Damdgpu_dev_coredump.c49 [MMHUB_HWIP] = "MMHUB",
278 fault_info->vmhub ? "mmhub" : "gfxhub"); in amdgpu_devcoredump_read()
H A Damdgpu_gmc.c541 /* mmhub ras block */ in amdgpu_gmc_ras_sw_init()
608 /* reserve mmhub engine 3 for firmware */ in amdgpu_gmc_allocate_vm_inv_eng()
973 RREG32_SOC15_IP(MMHUB, reg); in amdgpu_gmc_set_vm_fault_masks()
982 WREG32_SOC15_IP(MMHUB, reg, tmp); in amdgpu_gmc_set_vm_fault_masks()
/linux/drivers/gpu/drm/amd/include/ivsrcid/vpe/
H A Dirqsrcs_vpe_6_1.h35 #define VPE_6_1_SRCID__VPE_NACK_GEN_ERR 9 // 0x9 MMHUB return general…
36 #define VPE_6_1_SRCID__VPE_NACK_PRT 10 // 0xA MMHUB return PRT (na…
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v13_0_4_ppsmc.h104 #define PPSMC_MSG_IspStutterOn_MmhubPgDis 0x2F ///< ISP StutterOn mmHub PgDis
105 #define PPSMC_MSG_IspStutterOff_MmhubPgEn 0x30 ///< ISP StufferOff mmHub PgEn
H A Dsmu13_driver_if_v13_0_6.h69 // MMHUB
H A Dsmu14_driver_if_v14_0.h1403 // Padding for MMHUB - do not modify this
1516 // Padding for MMHUB - do not modify this
1590 // Padding for MMHUB - do not modify this
H A Dsmu13_driver_if_v13_0_0.h1271 // Padding for MMHUB - do not modify this
1367 // Padding for MMHUB - do not modify this
H A Dsmu13_driver_if_v13_0_7.h1265 // Padding for MMHUB - do not modify this
1360 // Padding for MMHUB - do not modify this
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_factory_dcn30.c47 #include "mmhub/mmhub_2_0_0_offset.h"
48 #include "mmhub/mmhub_2_0_0_sh_mask.h"
H A Dhw_translate_dcn30.c45 #include "mmhub/mmhub_2_0_0_offset.h"
46 #include "mmhub/mmhub_2_0_0_sh_mask.h"
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c44 #include "mmhub/mmhub_2_0_0_offset.h"
45 #include "mmhub/mmhub_2_0_0_sh_mask.h"

12