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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v4_2_0.c27 #include "mmhub/mmhub_4_2_0_offset.h"
28 #include "mmhub/mmhub_4_2_0_sh_mask.h"
79 base = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), in mmhub_v4_2_0_get_fb_location()
85 RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), in mmhub_v4_2_0_get_fb_location()
93 return (u64)RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), in mmhub_v4_2_0_get_mc_fb_offset()
107 WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_setup_vm_pt_regs()
112 WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_setup_vm_pt_regs()
146 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs()
149 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs()
153 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs()
[all …]
H A Dmmhub_v1_0.c27 #include "mmhub/mmhub_1_0_offset.h"
28 #include "mmhub/mmhub_1_0_sh_mask.h"
29 #include "mmhub/mmhub_1_0_default.h"
39 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); in mmhub_v1_0_get_fb_location()
40 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP); in mmhub_v1_0_get_fb_location()
59 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v1_0_setup_vm_pt_regs()
63 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v1_0_setup_vm_pt_regs()
74 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v1_0_init_gart_aperture_regs()
76 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v1_0_init_gart_aperture_regs()
79 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v1_0_init_gart_aperture_regs()
[all …]
H A Dmmhub_v2_3.c27 #include "mmhub/mmhub_2_3_0_offset.h"
28 #include "mmhub/mmhub_2_3_0_sh_mask.h"
29 #include "mmhub/mmhub_2_3_0_default.h"
127 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v2_3_setup_vm_pt_regs()
130 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v2_3_setup_vm_pt_regs()
140 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v2_3_init_gart_aperture_regs()
142 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v2_3_init_gart_aperture_regs()
145 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v2_3_init_gart_aperture_regs()
147 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v2_3_init_gart_aperture_regs()
157 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); in mmhub_v2_3_init_system_aperture_regs()
[all …]
H A Dmmhub_v4_1_0.c27 #include "mmhub/mmhub_4_1_0_offset.h"
28 #include "mmhub/mmhub_4_1_0_sh_mask.h"
75 /* Only use legacy inv on mmhub side */ in mmhub_v4_1_0_get_invalidate_req()
134 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v4_1_0_setup_vm_pt_regs()
138 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v4_1_0_setup_vm_pt_regs()
149 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v4_1_0_init_gart_aperture_regs()
151 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v4_1_0_init_gart_aperture_regs()
154 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v4_1_0_init_gart_aperture_regs()
156 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v4_1_0_init_gart_aperture_regs()
174 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); in mmhub_v4_1_0_init_system_aperture_regs()
[all …]
H A Dmmhub_v3_0.c27 #include "mmhub/mmhub_3_0_0_offset.h"
28 #include "mmhub/mmhub_3_0_0_sh_mask.h"
142 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v3_0_setup_vm_pt_regs()
146 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v3_0_setup_vm_pt_regs()
157 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v3_0_init_gart_aperture_regs()
159 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v3_0_init_gart_aperture_regs()
162 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v3_0_init_gart_aperture_regs()
164 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v3_0_init_gart_aperture_regs()
182 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); in mmhub_v3_0_init_system_aperture_regs()
183 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_init_system_aperture_regs()
[all …]
H A Dmmhub_v3_0_1.c27 #include "mmhub/mmhub_3_0_1_offset.h"
28 #include "mmhub/mmhub_3_0_1_sh_mask.h"
151 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v3_0_1_setup_vm_pt_regs()
155 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v3_0_1_setup_vm_pt_regs()
166 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v3_0_1_init_gart_aperture_regs()
168 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v3_0_1_init_gart_aperture_regs()
171 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v3_0_1_init_gart_aperture_regs()
173 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v3_0_1_init_gart_aperture_regs()
183 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); in mmhub_v3_0_1_init_system_aperture_regs()
184 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_1_init_system_aperture_regs()
[all …]
H A Dmmhub_v3_0_2.c27 #include "mmhub/mmhub_3_0_2_offset.h"
28 #include "mmhub/mmhub_3_0_2_sh_mask.h"
135 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v3_0_2_setup_vm_pt_regs()
139 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v3_0_2_setup_vm_pt_regs()
150 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v3_0_2_init_gart_aperture_regs()
152 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v3_0_2_init_gart_aperture_regs()
155 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v3_0_2_init_gart_aperture_regs()
157 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v3_0_2_init_gart_aperture_regs()
167 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); in mmhub_v3_0_2_init_system_aperture_regs()
168 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_2_init_system_aperture_regs()
[all …]
H A Dmmhub_v2_0.c27 #include "mmhub/mmhub_2_0_0_offset.h"
28 #include "mmhub/mmhub_2_0_0_sh_mask.h"
29 #include "mmhub/mmhub_2_0_0_default.h"
195 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v2_0_setup_vm_pt_regs()
199 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v2_0_setup_vm_pt_regs()
210 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
212 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
215 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
217 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
228 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); in mmhub_v2_0_init_system_aperture_regs()
[all …]
H A Damdgpu_mmhub.c29 if (!adev->mmhub.ras) in amdgpu_mmhub_ras_sw_init()
32 ras = adev->mmhub.ras; in amdgpu_mmhub_ras_sw_init()
35 dev_err(adev->dev, "Failed to register mmhub ras block!\n"); in amdgpu_mmhub_ras_sw_init()
39 strcpy(ras->ras_block.ras_comm.name, "mmhub"); in amdgpu_mmhub_ras_sw_init()
42 adev->mmhub.ras_if = &ras->ras_block.ras_comm; in amdgpu_mmhub_ras_sw_init()
44 /* mmhub ras follows amdgpu_ras_block_late_init_default for late init */ in amdgpu_mmhub_ras_sw_init()
H A Dimu_v12_0.c33 #include "mmhub/mmhub_4_1_0_offset.h"
309 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in imu_v12_init_gfxhub_settings()
311 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_TOP); in imu_v12_init_gfxhub_settings()
313 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET); in imu_v12_init_gfxhub_settings()
315 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE); in imu_v12_init_gfxhub_settings()
317 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT); in imu_v12_init_gfxhub_settings()
319 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP); in imu_v12_init_gfxhub_settings()
321 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in imu_v12_init_gfxhub_settings()
323 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR); in imu_v12_init_gfxhub_settings()
325 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR); in imu_v12_init_gfxhub_settings()
[all …]
H A Dgmc_v9_0.c38 #include "mmhub/mmhub_1_0_offset.h"
333 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
334 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
495 tmp = RREG32_SOC15_IP(MMHUB, reg); in gmc_v9_0_vm_fault_interrupt_state()
502 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
523 tmp = RREG32_SOC15_IP(MMHUB, reg); in gmc_v9_0_vm_fault_interrupt_state()
530 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
860 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
873 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
888 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
[all …]
H A Damdgpu_dev_coredump.c49 [MMHUB_HWIP] = "MMHUB",
278 fault_info->vmhub ? "mmhub" : "gfxhub"); in amdgpu_devcoredump_read()
H A Damdgpu_amdkfd_gfx_v9.c115 * need to do this twice, once for gfx and once for mmhub in kgd_gfx_v9_set_pasid_vmid_mapping()
116 * for ATC add 16 to VMID for mmhub, for IH different registers. in kgd_gfx_v9_set_pasid_vmid_mapping()
922 adev->mmhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); in kgd_gfx_v9_set_vm_context_page_table_base()
H A Damdgpu_gmc.c589 /* mmhub ras block */ in amdgpu_gmc_ras_sw_init()
656 /* reserve mmhub engine 3 for firmware */ in amdgpu_gmc_allocate_vm_inv_eng()
1022 RREG32_SOC15_IP(MMHUB, reg); in amdgpu_gmc_set_vm_fault_masks()
1031 WREG32_SOC15_IP(MMHUB, reg, tmp); in amdgpu_gmc_set_vm_fault_masks()
/linux/drivers/gpu/drm/amd/include/ivsrcid/vpe/
H A Dirqsrcs_vpe_6_1.h35 #define VPE_6_1_SRCID__VPE_NACK_GEN_ERR 9 // 0x9 MMHUB return general…
36 #define VPE_6_1_SRCID__VPE_NACK_PRT 10 // 0xA MMHUB return PRT (na…
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v13_0_4_ppsmc.h104 #define PPSMC_MSG_IspStutterOn_MmhubPgDis 0x2F ///< ISP StutterOn mmHub PgDis
105 #define PPSMC_MSG_IspStutterOff_MmhubPgEn 0x30 ///< ISP StufferOff mmHub PgEn
H A Dsmu13_driver_if_v13_0_6.h69 // MMHUB
H A Dsmu14_driver_if_v14_0.h1403 // Padding for MMHUB - do not modify this
1516 // Padding for MMHUB - do not modify this
1590 // Padding for MMHUB - do not modify this
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_factory_dcn30.c47 #include "mmhub/mmhub_2_0_0_offset.h"
48 #include "mmhub/mmhub_2_0_0_sh_mask.h"
H A Dhw_translate_dcn30.c45 #include "mmhub/mmhub_2_0_0_offset.h"
46 #include "mmhub/mmhub_2_0_0_sh_mask.h"
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c41 #include "mmhub/mmhub_2_0_0_offset.h"
42 #include "mmhub/mmhub_2_0_0_sh_mask.h"
/linux/drivers/gpu/drm/amd/ras/rascore/
H A Dras_aca_v1_0.c168 /* Check MMHUB error codes */ in aca_match_mmhub_bank()
347 .name = "mmhub",
/linux/drivers/gpu/drm/amd/display/dc/resource/dce120/
H A Ddce120_resource.c65 #include "mmhub/mmhub_1_0_offset.h"
66 #include "mmhub/mmhub_1_0_sh_mask.h"
145 /* MMHUB */
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c44 #include "mmhub/mmhub_2_0_0_offset.h"
45 #include "mmhub/mmhub_2_0_0_sh_mask.h"
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c68 #include "mmhub/mmhub_2_0_0_offset.h"
69 #include "mmhub/mmhub_2_0_0_sh_mask.h"
290 /* MMHUB */

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