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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v1_0.c27 #include "mmhub/mmhub_1_0_offset.h"
28 #include "mmhub/mmhub_1_0_sh_mask.h"
29 #include "mmhub/mmhub_1_0_default.h"
39 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); in mmhub_v1_0_get_fb_location()
40 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP); in mmhub_v1_0_get_fb_location()
59 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v1_0_setup_vm_pt_regs()
63 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v1_0_setup_vm_pt_regs()
74 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v1_0_init_gart_aperture_regs()
76 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v1_0_init_gart_aperture_regs()
79 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v1_0_init_gart_aperture_regs()
[all …]
H A Dmmhub_v2_3.c27 #include "mmhub/mmhub_2_3_0_offset.h"
28 #include "mmhub/mmhub_2_3_0_sh_mask.h"
29 #include "mmhub/mmhub_2_3_0_default.h"
93 mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); in mmhub_v2_3_print_l2_protection_fault_status()
117 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v2_3_setup_vm_pt_regs()
120 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v2_3_setup_vm_pt_regs()
130 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v2_3_init_gart_aperture_regs()
132 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v2_3_init_gart_aperture_regs()
135 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v2_3_init_gart_aperture_regs()
137 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v2_3_init_gart_aperture_regs()
[all …]
H A Dmmhub_v2_0.c27 #include "mmhub/mmhub_2_0_0_offset.h"
28 #include "mmhub/mmhub_2_0_0_sh_mask.h"
29 #include "mmhub/mmhub_2_0_0_default.h"
154 mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); in mmhub_v2_0_print_l2_protection_fault_status()
177 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v2_0_setup_vm_pt_regs()
181 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v2_0_setup_vm_pt_regs()
192 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
194 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
197 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
199 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
[all …]
H A Damdgpu_mmhub.c29 if (!adev->mmhub.ras) in amdgpu_mmhub_ras_sw_init()
32 ras = adev->mmhub.ras; in amdgpu_mmhub_ras_sw_init()
35 dev_err(adev->dev, "Failed to register mmhub ras block!\n"); in amdgpu_mmhub_ras_sw_init()
39 strcpy(ras->ras_block.ras_comm.name, "mmhub"); in amdgpu_mmhub_ras_sw_init()
42 adev->mmhub.ras_if = &ras->ras_block.ras_comm; in amdgpu_mmhub_ras_sw_init()
44 /* mmhub ras follows amdgpu_ras_block_late_init_default for late init */ in amdgpu_mmhub_ras_sw_init()
H A Dgmc_v11_0.c145 entry->vmid_src ? "mmhub" : "gfxhub", in gmc_v11_0_process_interrupt()
294 /* Issue additional private vm invalidation to MMHUB */ in gmc_v11_0_flush_gpu_tlb()
579 adev->mmhub.funcs = &mmhub_v3_0_1_funcs; in gmc_v11_0_set_mmhub_funcs()
582 adev->mmhub.funcs = &mmhub_v3_0_2_funcs; in gmc_v11_0_set_mmhub_funcs()
589 adev->mmhub.funcs = &mmhub_v3_3_funcs; in gmc_v11_0_set_mmhub_funcs()
592 adev->mmhub.funcs = &mmhub_v3_0_funcs; in gmc_v11_0_set_mmhub_funcs()
657 base = adev->mmhub.funcs->get_fb_location(adev); in gmc_v11_0_vram_gtt_location()
671 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); in gmc_v11_0_vram_gtt_location()
702 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); in gmc_v11_0_mc_init()
745 adev->mmhub.funcs->init(adev); in gmc_v11_0_sw_init()
[all …]
H A Dgmc_v12_1.c55 tmp = RREG32_SOC15_IP(MMHUB, reg); in gmc_v12_1_vm_fault_interrupt_state()
62 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v12_1_vm_fault_interrupt_state()
83 tmp = RREG32_SOC15_IP(MMHUB, reg); in gmc_v12_1_vm_fault_interrupt_state()
90 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v12_1_vm_fault_interrupt_state()
330 /* Issue additional private vm invalidation to MMHUB */ in gmc_v12_1_flush_vm_hub()
H A Damdgpu_amdkfd_gfx_v9.c115 * need to do this twice, once for gfx and once for mmhub in kgd_gfx_v9_set_pasid_vmid_mapping()
116 * for ATC add 16 to VMID for mmhub, for IH different registers. in kgd_gfx_v9_set_pasid_vmid_mapping()
922 adev->mmhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); in kgd_gfx_v9_set_vm_context_page_table_base()
H A Damdgpu_dev_coredump.c58 [MMHUB_HWIP] = "MMHUB",
425 fault_info->vmhub ? "mmhub" : "gfxhub"); in amdgpu_devcoredump_format()
H A Damdgpu_gmc.c602 /* mmhub ras block */ in amdgpu_gmc_ras_sw_init()
659 /* reserve mmhub engine 3 for firmware */ in amdgpu_gmc_allocate_vm_inv_eng()
1034 RREG32_SOC15_IP(MMHUB, reg); in amdgpu_gmc_set_vm_fault_masks()
1043 WREG32_SOC15_IP(MMHUB, reg, tmp); in amdgpu_gmc_set_vm_fault_masks()
H A Djpeg_v4_0_3.c765 /* PCTL0__MMHUB_DEEPSLEEP_IB could be different on different mmhub version */ in jpeg_v4_0_3_dec_ring_insert_start()
806 /* PCTL0__MMHUB_DEEPSLEEP_IB could be different on different mmhub version */ in jpeg_v4_0_3_dec_ring_insert_end()
H A Dpsp_gfx_if.h113 GFX_CMD_ID_SET_MMHUB_ECO_SEC_LEVEL = 0x0000005D, /* Set MMHUB ECO sec lvls on VCN block */
H A Dih_v6_1.c339 /* GC/MMHUB UTCL2 page fault interrupts are configured as in ih_v6_1_irq_init()
H A Damdgpu_amdkfd_gfx_v10.c129 pr_debug("update mapping for IH block and mmhub"); in kgd_set_pasid_vmid_mapping()
/linux/drivers/gpu/drm/amd/include/ivsrcid/vpe/
H A Dirqsrcs_vpe_6_1.h35 #define VPE_6_1_SRCID__VPE_NACK_GEN_ERR 9 // 0x9 MMHUB return general…
36 #define VPE_6_1_SRCID__VPE_NACK_PRT 10 // 0xA MMHUB return PRT (na…
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v13_0_4_ppsmc.h104 #define PPSMC_MSG_IspStutterOn_MmhubPgDis 0x2F ///< ISP StutterOn mmHub PgDis
105 #define PPSMC_MSG_IspStutterOff_MmhubPgEn 0x30 ///< ISP StufferOff mmHub PgEn
H A Dsmu13_driver_if_v13_0_6.h69 // MMHUB
H A Dsmu14_driver_if_v14_0.h1403 // Padding for MMHUB - do not modify this
1516 // Padding for MMHUB - do not modify this
1590 // Padding for MMHUB - do not modify this
H A Dsmu13_driver_if_v13_0_0.h1271 // Padding for MMHUB - do not modify this
1367 // Padding for MMHUB - do not modify this
H A Dsmu13_driver_if_v13_0_7.h1265 // Padding for MMHUB - do not modify this
1360 // Padding for MMHUB - do not modify this
H A Dsmu11_driver_if_sienna_cichlid.h957 // Padding for MMHUB - do not modify this
1318 // Padding for MMHUB - do not modify this
H A Dsmu11_driver_if_arcturus.h733 // Padding for MMHUB - do not modify this
H A Dsmu11_driver_if_navi10.h814 // Padding for MMHUB - do not modify this
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_factory_dcn30.c47 #include "mmhub/mmhub_2_0_0_offset.h"
48 #include "mmhub/mmhub_2_0_0_sh_mask.h"
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c88 #include "mmhub/mmhub_2_3_0_offset.h"
89 #include "mmhub/mmhub_2_3_0_sh_mask.h"
182 /* MMHUB */
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c82 #include "mmhub/mmhub_2_0_0_offset.h"
83 #include "mmhub/mmhub_2_0_0_sh_mask.h"
171 /* MMHUB */

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