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/linux/drivers/gpu/drm/vmwgfx/
H A Dvmw_surface_cache.h310 * @bytes: Bytes required in the backing store of this mipmap level.
313 * @size: The size of the mipmap.
326 * @mip: Array of mipmap level information. Valid size is @num_mip_levels.
331 * @num_mip_levels: Valid size of the @mip array. Number of mipmap levels in
361 * vmw_surface_subres - Compute the subresource from layer and mipmap.
363 * @mip_level: The mipmap level.
378 * @num_mip_levels: Number of mipmap levels.
H A Dvmwgfx_cursor_plane.c344 if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) { in vmw_kms_cursor_snoop()
345 DRM_ERROR("face and mipmap for cursors should never != 0\n"); in vmw_kms_cursor_snoop()
H A Dvmwgfx_surface.c303 body->host.mipmap = cur_offset->mip; in vmw_surface_dma_encode()
1984 cmd2->body.image.mipmap = i - in vmw_surface_dirty_sync()
H A Dvmwgfx_stdu.c1211 cmd_img->body.image.mipmap = 0; in vmw_stdu_bo_populate_update_cpu()
/linux/drivers/gpu/drm/radeon/
H A Dr600_cs.c1466 * @mipmap: mipmap's bo structure
1472 * the texture and mipmap bo object are big enough to cover this resource.
1476 struct radeon_bo *mipmap, in r600_check_texture_resource() argument
1607 /* using get ib will give us the offset into the mipmap bo */ in r600_check_texture_resource()
1608 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) { in r600_check_texture_resource()
1609 /*dev_warn_once(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", in r600_check_texture_resource()
1959 struct radeon_bo *texture, *mipmap; in r600_packet3_check() local
1985 mipmap = reloc->robj; in r600_packet3_check()
1987 texture, mipmap, in r600_packet3_check()
H A Devergreen_cs.c756 struct radeon_bo *mipmap, in evergreen_cs_track_validate_texture() argument
844 dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_texture()
863 if (!mipmap) { in evergreen_cs_track_validate_texture()
873 /* check mipmap size */ in evergreen_cs_track_validate_texture()
903 r = evergreen_surface_check(p, &surf, "mipmap"); in evergreen_cs_track_validate_texture()
913 if (moffset > radeon_bo_size(mipmap)) { in evergreen_cs_track_validate_texture()
914 dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, " in evergreen_cs_track_validate_texture()
919 d, radeon_bo_size(mipmap), in evergreen_cs_track_validate_texture()
2349 struct radeon_bo *texture, *mipmap; in evergreen_packet3_check() local
2391 mipmap = NULL; in evergreen_packet3_check()
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/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da5xx.xml2206 Example Layout 2d w/ mipmap levels:
2791 like 2nd source for blending? Used in mipmap generation.. but
2948 <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
2956 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
2957 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
2959 higher (smaller) mipmap levels
H A Da3xx.xml1728 <!-- minimum pitch (for mipmap levels): log2(pitchalign / 16) -->
1732 <doc>INDX is index of texture address(es) in MIPMAP state block</doc>
H A Dadreno_pm4.xml515 General purpose 2D blit engine for image transfers and mipmap
1730 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
H A Da4xx.xml2355 <!-- minimum pitch (for mipmap levels): log2(pitchalign / 32) -->
/linux/drivers/gpu/drm/vmwgfx/device_include/
H A Dsvga3d_types.h1451 uint32 mipmap; member
/linux/include/uapi/drm/
H A Dvmwgfx_drm.h197 * The size of the array should equal the total number of mipmap levels.