Searched +full:min +full:- +full:output +full:- +full:impedance (Results 1 – 9 of 9) sorted by relevance
23 * o JEDEC JEP-106 vendor data25 * (JESD402-1)47 * JEDEC operating temperature ranges. These are defined in JESD402-1B127 * parse the overall SPD data structure. These represent a top-level failure and162 * categories. Fatal errors set a value in the spd_error_t below. Non-fatal166 * The keys are all dot delineated to create a few different top-level169 * "meta" -- Which includes information about the SPD, encoding, and things like172 * "dram" -- Parameters that are specific to the SDRAM dies present. What one177 * "channel" -- Parameters that are tied to an implementation of a channel. DDR4179 * sub-channels.[all …]
12 * are provided to you under the BSD-type license terms provided17 * - Redistributions of source code must retain the above copyright19 * - Redistributions in binary form must reproduce the above23 * - Neither the name of Marvell nor the names of its contributors57 * D-Link PCI vendor ID91 * D-Link gigabit ethernet device ID133 #define PCI_Y2_PIG_ENA BIT(31) /* Enable Plug-in-Go (YUKON-2) */134 #define PCI_Y2_DLL_DIS BIT(30) /* Disable PCI DLL (YUKON-2) */135 #define PCI_Y2_PHY2_COMA BIT(29) /* Set PHY 2 to Coma Mode (YUKON-2) */136 #define PCI_Y2_PHY1_COMA BIT(28) /* Set PHY 1 to Coma Mode (YUKON-2) */[all …]
3 …//ACCESS:RW DataWidth:0x2 Description: Defines the number of sets - 3 - 256 ;2- 128; 1- 64; 0- 329 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…10 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…11 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…12 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…13 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…14 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…15 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…16 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…17 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…[all …]
9 * or http://opensource.org/licenses/CDDL-1.0.23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.060 … 0x001d14UL //Access:RW DataWidth:0x8 DBMUX register for selecting a line to output Chips: K2 61 … in the selected line (before shift).for selecting a line to output Chips: K2 85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…144 …_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message s…[all …]
9 * or http://opensource.org/licenses/CDDL-1.0.23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.060 … 0x001d14UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output61 … line) in the selected line (before shift).for selecting a line to output84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …[all …]
9 * or http://opensource.org/licenses/CDDL-1.0.23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.060 … 0x001d14UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output61 … line) in the selected line (before shift).for selecting a line to output85 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…86 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…87 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…88 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…90 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …[all …]
2 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved.33 /* Power-on reset state */55 /* The 'doorbell' addresses are hard-wired to alert the MC when written */58 /* The rest of these are firmware-defined */66 /* Values to be written to the per-port status dword in shared95 * | | \--- Response96 * | \------- Error97 * \------------------------------ Resync (always set)152 * - To complete a shared memory request if XFLAGS_EVREQ was set153 * - As a notification (link state, i2c event), controlled[all …]