| /linux/drivers/memory/ |
| H A D | pl353-smc.c | 20 * @memclk: Pointer to the peripheral clock
24 struct clk *memclk; member
32 clk_disable(pl353_smc->memclk); in pl353_smc_suspend()
49 ret = clk_enable(pl353_smc->memclk); in pl353_smc_resume()
87 pl353_smc->memclk = devm_clk_get_enabled(&adev->dev, "memclk"); in pl353_smc_probe()
88 if (IS_ERR(pl353_smc->memclk)) in pl353_smc_probe()
89 return dev_err_probe(&adev->dev, PTR_ERR(pl353_smc->memclk), in pl353_smc_probe()
90 "memclk clock not found.\n"); in pl353_smc_probe()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 303 * Send message to PMFW to set hard min memclk frequency
309 /* Send message to PMFW to set hard max memclk frequency to highest DPM */
312 /* Custom set a memclk freq range*/
316 /* Get current memclk states from PMFW, update relevant structures */
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | arm,pl35x-smc.yaml | 134 - const: memclk
142 clock-names = "memclk", "apb_pclk";
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 591 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; in vg_clk_mgr_helper_populate_bw_params()
596 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; in vg_clk_mgr_helper_populate_bw_params()
632 { .fclk = 400, .memclk = 400, .voltage = 2800 },
633 { .fclk = 400, .memclk = 400, .voltage = 2800 },
634 { .fclk = 400, .memclk = 400, .voltage = 2800 },
635 { .fclk = 400, .memclk = 400, .voltage = 2800 }
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| H A D | dcn301_smu.h | 33 uint32_t memclk; member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 354 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
375 /* Set max memclk to highest DPM value */
405 /* Get current memclk states, update bounding box */
414 /* Refresh memclk states */ in dcn3_get_memclk_states_from_smu()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| H A D | smu14_driver_if_v14_0_0.h | 112 uint32_t MemClk; member
208 uint16_t MemclkFrequency; //Time filtered target MEMCLK frequency [MHz]
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| H A D | smu13_driver_if_v13_0_5.h | 79 uint32_t MemClk; member
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| H A D | smu13_driver_if_yellow_carp.h | 113 uint32_t MemClk; member
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| H A D | smu11_driver_if_vangogh.h | 115 uint32_t memclk; member
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| /linux/Documentation/devicetree/bindings/mtd/ |
| H A D | arm,pl353-nand-r2p1.yaml | 38 clock-names = "memclk", "apb_pclk";
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.c | 512 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk; in dcn315_clk_mgr_helper_populate_bw_params()
524 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[0].MemClk; in dcn315_clk_mgr_helper_populate_bw_params()
708 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n" in dcn315_clk_mgr_construct()
711 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk, in dcn315_clk_mgr_construct()
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| H A D | dcn315_smu.h | 63 uint32_t MemClk; member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_smu.h | 41 uint32_t MemClk; member
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| H A D | dcn314_clk_mgr.c | 673 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[min_pstate].MemClk; in dcn314_clk_mgr_helper_populate_bw_params()
689 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk; in dcn314_clk_mgr_helper_populate_bw_params()
892 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n" in dcn314_clk_mgr_construct()
895 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk, in dcn314_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 993 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
1014 /* Set max memclk to highest DPM value */
1025 /* Get current memclk states, update bounding box */
1035 /* Refresh memclk and fclk states */ in dcn32_get_memclk_states_from_smu()
1042 /* memclk must have at least one level */ in dcn32_get_memclk_states_from_smu()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_smu.h | 69 uint32_t MemClk; member
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| /linux/arch/arm/include/uapi/asm/ |
| H A D | setup.h | 168 struct tag_memclk memclk; member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.c | 596 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; in dcn31_clk_mgr_helper_populate_bw_params()
782 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n" in dcn31_clk_mgr_construct()
785 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk, in dcn31_clk_mgr_construct()
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| H A D | dcn31_smu.h | 122 uint32_t MemClk; member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_smu.h | 95 uint32_t MemClk; member
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| H A D | dcn35_clk_mgr.c | 854 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk; in dcn35_clk_mgr_helper_populate_bw_params()
873 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk; in dcn35_clk_mgr_helper_populate_bw_params()
1196 "smu_dpm_clks.dpm_clks->MemPstateTable[%d].MemClk= %d\n" in dcn35_clk_mgr_construct()
1199 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].MemClk, in dcn35_clk_mgr_construct()
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| /linux/arch/arm/mach-footbridge/ |
| H A D | common.c | 130 mem_fclk_21285 = tag->u.memclk.fmemclk; in parse_tag_memclk()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega20_hwmgr.c | 625 "[SetupDefaultDpmTable] failed to get memclk dpm levels!", in vega20_setup_memclk_dpm_table()
672 /* memclk */ in vega20_setup_default_dpm_tables()
1556 "[SetMclkOD] failed to set od memclk!", in vega20_set_mclk_od()
1559 /* retrieve updated memclk table */ in vega20_set_mclk_od()
1562 "[SetMclkOD] failed to refresh memclk table!", in vega20_set_mclk_od()
1845 "Failed to set soft min memclk !", in vega20_upload_dpm_min_level()
1948 "Failed to set soft max memclk!", in vega20_upload_dpm_max_level()
2097 "[MemMclks]: memclk dpm not enabled!\n", in vega20_dpm_get_mclk()
3163 /* retrieve updated memclk table */ in vega20_odn_edit_dpm_table()
3777 /* memclk */ in vega20_apply_clocks_adjust_rules()
[all …]
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| /linux/arch/arm/kernel/ |
| H A D | atags_compat.c | 165 tag->u.memclk.fmemclk = params->u1.s.mem_fclk_21285; in build_tag_list()
|