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Searched full:mast (Results 1 – 8 of 8) sorted by relevance

/linux/lib/
H A Dmaple_tree.c2232 * @mast: The maple subtree state
2234 static inline void mast_rebalance_next(struct maple_subtree_state *mast) in mast_rebalance_next() argument
2236 unsigned char b_end = mast->bn->b_end; in mast_rebalance_next()
2238 mas_mab_cp(mast->orig_r, 0, mt_slot_count(mast->orig_r->node), in mast_rebalance_next()
2239 mast->bn, b_end); in mast_rebalance_next()
2240 mast->orig_r->last = mast->orig_r->max; in mast_rebalance_next()
2245 * @mast: The maple subtree state
2247 static inline void mast_rebalance_prev(struct maple_subtree_state *mast) in mast_rebalance_prev() argument
2249 unsigned char end = mas_data_end(mast->orig_l) + 1; in mast_rebalance_prev()
2250 unsigned char b_end = mast->bn->b_end; in mast_rebalance_prev()
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H A Dtest_maple_tree.c2264 * Fixed by setting mast->r->max correctly. in check_fuzzer()
2312 * Fixed by setting mast->r->max correctly in mast_cp_to_nodes() in check_fuzzer()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dmcp77.c86 u32 mast = nvkm_rd32(device, 0x00c054); in mcp77_clk_read() local
99 switch (mast & 0x000c0000) { in mcp77_clk_read()
109 switch (mast & 0x00000003) { in mcp77_clk_read()
117 if ((mast & 0x03000000) != 0x03000000) in mcp77_clk_read()
120 if ((mast & 0x00000200) == 0x00000000) in mcp77_clk_read()
123 switch (mast & 0x00000c00) { in mcp77_clk_read()
131 switch (mast & 0x00000030) { in mcp77_clk_read()
133 if (mast & 0x00000040) in mcp77_clk_read()
146 switch (mast & 0x00400000) { in mcp77_clk_read()
157 nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast); in mcp77_clk_read()
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H A Dnv50.c129 u32 src, mast = nvkm_rd32(device, 0x00c040); in read_pll_ref() local
133 src = !!(mast & 0x00200000); in read_pll_ref()
136 src = !!(mast & 0x00400000); in read_pll_ref()
139 src = !!(mast & 0x00010000); in read_pll_ref()
142 src = !!(mast & 0x02000000); in read_pll_ref()
161 u32 mast = nvkm_rd32(device, 0x00c040); in read_pll() local
168 if (base == 0x004028 && (mast & 0x00100000)) { in read_pll()
197 u32 mast = nvkm_rd32(device, 0x00c040); in nv50_clk_read() local
212 switch (mast & 0x30000000) { in nv50_clk_read()
220 if (!(mast & 0x00100000)) in nv50_clk_read()
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H A Dnv40.c102 u32 mast = nvkm_rd32(device, 0x00c040); in nv40_clk_read() local
110 return read_clk(clk, (mast & 0x00000003) >> 0); in nv40_clk_read()
112 return read_clk(clk, (mast & 0x00000030) >> 4); in nv40_clk_read()
119 nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast); in nv40_clk_read()
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmicrochip,sparx5-sgpio.yaml47 even. The tuples mast be ordered (low, high) and are
/linux/drivers/zorro/
H A Dzorro.ids460 0800 MAST Fireball [SCSI Host Adapter]
/linux/drivers/net/wireless/ath/ath10k/
H A Dhtt.h74 * but the host shall use the bit-mast + bit-shift defs, to be endian-