Lines Matching full:mast
129 u32 src, mast = nvkm_rd32(device, 0x00c040); in read_pll_ref() local
133 src = !!(mast & 0x00200000); in read_pll_ref()
136 src = !!(mast & 0x00400000); in read_pll_ref()
139 src = !!(mast & 0x00010000); in read_pll_ref()
142 src = !!(mast & 0x02000000); in read_pll_ref()
161 u32 mast = nvkm_rd32(device, 0x00c040); in read_pll() local
168 if (base == 0x004028 && (mast & 0x00100000)) { in read_pll()
197 u32 mast = nvkm_rd32(device, 0x00c040); in nv50_clk_read() local
212 switch (mast & 0x30000000) { in nv50_clk_read()
220 if (!(mast & 0x00100000)) in nv50_clk_read()
222 switch (mast & 0x00000003) { in nv50_clk_read()
231 switch (mast & 0x00000030) { in nv50_clk_read()
233 if (mast & 0x00000080) in nv50_clk_read()
244 switch (mast & 0x0000c000) { in nv50_clk_read()
264 switch (mast & 0x00000c00) { in nv50_clk_read()
272 if (mast & 0x01000000) in nv50_clk_read()
280 switch (mast & 0x00000c00) { in nv50_clk_read()
305 switch (mast & 0x0c000000) { in nv50_clk_read()
321 nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast); in nv50_clk_read()
447 clk_mask(hwsq, mast, mastm, 0x00000000); in nv50_clk_calc()
449 clk_mask(hwsq, mast, mastm, mastv); in nv50_clk_calc()
455 clk_mask(hwsq, mast, 0x001000b0, 0x00100080); in nv50_clk_calc()
457 clk_mask(hwsq, mast, 0x000000b3, 0x00000081); in nv50_clk_calc()
476 clk_mask(hwsq, mast, 0x00100033, 0x00000023); in nv50_clk_calc()
485 clk_mask(hwsq, mast, 0x00100033, 0x00000033); in nv50_clk_calc()