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Searched +full:manual +full:- +full:strobe (Results 1 – 8 of 8) sorted by relevance

/freebsd/share/examples/ppi/
H A Dppilcd.c43 #define MAX_DRVOPT 10 /* maximum driver-specific options */
62 " 1 1-line display (default 2)",
108 while ((ch = getopt(argc, argv, "Dd:f:o:v")) != -1) { in main()
129 argc -= optind; in main()
146 debug(1, "Driver selected for %s", driver->l_name); in main()
147 driver->l_prepare(devname, drvopts); in main()
148 atexit(driver->l_finish); in main()
169 … fprintf(stderr, "usage: %s [-v] [-d drivername] [-f device] [-o options] [args...]\n", progname); in usage()
170 fprintf(stderr, " -D Increase debugging\n"); in usage()
171 fprintf(stderr, " -f Specify device, default is '%s'\n", DEFAULT_DEVICE); in usage()
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/freebsd/share/man/man4/
H A Dppbus.442 system provides a uniform, modular and architecture-independent
48 .Bl -bullet -offset indent
50 architecture-independent macros or functions to access parallel ports
57 with kernel-in drivers.
61 and non-standard software:
63 .Bl -column "Driver" -compact
67 .It Sy lpbb Ta "Philips official parallel port I2C bit-banging interface"
73 .Bl -column "Driver" -compact
100 .Bl -bullet -offset indent
104 bidirectional 8/4-bits mode, also called NIBBLE mode
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/freebsd/share/man/man9/
H A Dmicroseq.942 .Bl -enum -offset indent
69 In any other mode, drivers may be tri-stated by
74 This read-only register reflects the inputs on the parallel port interface.
76 .Bl -column "Bit" "Name" "Description" -compact
90 .Bl -column "Bit" "Name " "Description" -compact
97 .It 0 Ta STROBE Ta "inverted and driven as parallel port nStrobe signal"
108 .Bd -literal
134 .Bl -bullet -offset indent
151 are microinstructions used to do either predefined standard IEEE1284-1994
152 transfers or programmed non-standard io.
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/freebsd/sys/dev/ppbus/
H A Dlpt.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
35 * ON-LINE 386BSD USER MANUAL BEFORE USE. A BOOK DISCUSSING THE INTERNALS
112 /* default case: negative prime, negative ack, handshake strobe,
165 /* Printer Ready condition - from lpa.c */
202 if (sc->sc_state & HAVEBUS) in lpt_request_ppbus()
207 sc->sc_state |= HAVEBUS; in lpt_request_ppbus()
219 if (sc->sc_state & HAVEBUS) { in lpt_release_ppbus()
222 sc->sc_state &= ~HAVEBUS; in lpt_release_ppbus()
241 } while (temp != data && --timeout); in lpt_port_test()
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/freebsd/sys/dev/cadence/
H A Dif_cgem_hw.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2012-2013 Thomas Skibo
31 * controller such as the one used in Zynq-7000 SoC.
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
39 * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
244 #define CGEM_FRAMES_64B_TX 0x118 /* 64-Byte Frames xmitted */
245 #define CGEM_FRAMES_65_127B_TX 0x11C /* 65-127 Byte Frames xmitted*/
246 #define CGEM_FRAMES_128_255B_TX 0x120 /* 128-255 Byte Frames xmit */
247 #define CGEM_FRAMES_256_511B_TX 0x124 /* 256-511 Byte Frames xmit */
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/freebsd/sys/dev/rl/
H A Dif_rl.c1 /*-
16 * 4. Neither the name of the author nor the names of any co-contributors
48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
50 * gains that bus-master DMA usually offers.
54 * on a longword (32-bit) boundary. This means we almost always have to
57 * is 32-bit aligned within the mbuf's data area. The presence of only
72 * On the bright side, the 8139 does have a built-in PHY, although
75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * the 8139 lets you directly access the on-board PHY registers. We need
151 "D-Link DFE-520TX (rev. C1) 10/100BaseTX" },
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/freebsd/share/misc/
H A Dusb_vendors6 # http://www.linux-usb.org/usb-ids.html
7 # or send entries as patches (diff -u old new) in the
10 # http://www.linux-usb.org/usb.ids
13 # Date: 2024-07-04 20:34:02
20 # device device_name <-- single tab
21 # interface interface_name <-- two tabs
38 5301 GW-US54ZGL 802.11bg
54 145f NW-3100 802.11b/g 54Mbps Wireless Network Adapter [zd1211]
62 0200 TP-Link
81 120e ASI120MC-S Planetary Camera
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
78- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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