Lines Matching +full:manual +full:- +full:strobe
1 /*-
16 * 4. Neither the name of the author nor the names of any co-contributors
48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
50 * gains that bus-master DMA usually offers.
54 * on a longword (32-bit) boundary. This means we almost always have to
57 * is 32-bit aligned within the mbuf's data area. The presence of only
72 * On the bright side, the 8139 does have a built-in PHY, although
75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * the 8139 lets you directly access the on-board PHY registers. We need
151 "D-Link DFE-520TX (rev. C1) 10/100BaseTX" },
153 "D-Link DFE-530TX+ 10/100BaseTX" },
155 "D-Link DFE-690TXD 10/100BaseTX" },
159 "Corega FEther CB-TXD" },
161 "Corega FEtherII CB-TXD" },
163 "Peppercon AG ROL-F" },
165 "Planex FNW-3603-TX" },
167 "Planex FNW-3800-TX" },
169 "Compaq HNE-300" },
171 "LevelOne FPC-0106TX" },
173 "Edimax EP-4103DL CardBus" }
217 * MII bit-bang glue
259 nitems(rl_devs) - 1);
279 d = addr | sc->rl_eecmd_read; in rl_eeprom_putbyte()
282 * Feed in each bit and strobe the clock. in rl_eeprom_putbyte()
355 * Read the MII serial port for the MII bit-bang module.
373 * Write the MII serial port for the MII bit-bang module.
395 if (sc->rl_type == RL_8139) { in rl_miibus_readreg()
424 device_printf(sc->rl_dev, "bad phy register\n"); in rl_miibus_readreg()
441 if (sc->rl_type == RL_8139) { in rl_miibus_writereg()
463 device_printf(sc->rl_dev, "bad phy register\n"); in rl_miibus_writereg()
483 mii = device_get_softc(sc->rl_miibus); in rl_miibus_statchg()
484 ifp = sc->rl_ifp; in rl_miibus_statchg()
489 sc->rl_flags &= ~RL_FLAG_LINK; in rl_miibus_statchg()
490 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == in rl_miibus_statchg()
492 switch (IFM_SUBTYPE(mii->mii_media_active)) { in rl_miibus_statchg()
495 sc->rl_flags |= RL_FLAG_LINK; in rl_miibus_statchg()
503 * Tx/Rx MACs for resolved speed, duplex and flow-control in rl_miibus_statchg()
518 hashes[1] |= (1 << (h - 32)); in rl_hash_maddr()
524 * Program the 64-bit multicast hash filter.
529 if_t ifp = sc->rl_ifp; in rl_rxfilter()
576 device_printf(sc->rl_dev, "reset never completed!\n"); in rl_reset()
602 if (vendor == t->rl_vid && devid == t->rl_did) { in rl_probe()
603 device_set_desc(dev, t->rl_name); in rl_probe()
626 ctx->rl_busaddr = segs[0].ds_addr; in rl_dmamap_cb()
650 sc->rl_dev = dev; in rl_attach()
652 sc->rl_twister_enable = 0; in rl_attach()
654 TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable); in rl_attach()
655 ctx = device_get_sysctl_ctx(sc->rl_dev); in rl_attach()
656 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); in rl_attach()
658 &sc->rl_twister_enable, 0, ""); in rl_attach()
660 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, in rl_attach()
662 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); in rl_attach()
679 sc->rl_res_id = PCIR_BAR(0); in rl_attach()
680 sc->rl_res_type = SYS_RES_IOPORT; in rl_attach()
681 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, in rl_attach()
682 &sc->rl_res_id, RF_ACTIVE); in rl_attach()
684 if (prefer_iomap == 0 || sc->rl_res == NULL) { in rl_attach()
685 sc->rl_res_id = PCIR_BAR(1); in rl_attach()
686 sc->rl_res_type = SYS_RES_MEMORY; in rl_attach()
687 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, in rl_attach()
688 &sc->rl_res_id, RF_ACTIVE); in rl_attach()
690 if (sc->rl_res == NULL) { in rl_attach()
703 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF) in rl_attach()
708 sc->rl_btag = rman_get_bustag(sc->rl_res); in rl_attach()
709 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); in rl_attach()
713 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, in rl_attach()
716 if (sc->rl_irq[0] == NULL) { in rl_attach()
722 sc->rl_cfg0 = RL_8139_CFG0; in rl_attach()
723 sc->rl_cfg1 = RL_8139_CFG1; in rl_attach()
724 sc->rl_cfg2 = 0; in rl_attach()
725 sc->rl_cfg3 = RL_8139_CFG3; in rl_attach()
726 sc->rl_cfg4 = RL_8139_CFG4; in rl_attach()
727 sc->rl_cfg5 = RL_8139_CFG5; in rl_attach()
737 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; in rl_attach()
740 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; in rl_attach()
758 sc->rl_type = 0; in rl_attach()
759 while(t->rl_name != NULL) { in rl_attach()
760 if (rl_did == t->rl_did) { in rl_attach()
761 sc->rl_type = t->rl_basetype; in rl_attach()
767 if (sc->rl_type == 0) { in rl_attach()
770 sc->rl_type = RL_8139; in rl_attach()
782 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); in rl_attach()
788 if (sc->rl_type == RL_8139) in rl_attach()
790 error = mii_attach(dev, &sc->rl_miibus, ifp, rl_ifmedia_upd, in rl_attach()
806 if (sc->rl_type == RL_8139 && in rl_attach()
807 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) { in rl_attach()
838 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE, in rl_attach()
839 NULL, rl_intr, sc, &sc->rl_intrhand[0]); in rl_attach()
841 device_printf(sc->rl_dev, "couldn't set up irq\n"); in rl_attach()
866 ifp = sc->rl_ifp; in rl_detach()
868 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); in rl_detach()
879 callout_drain(&sc->rl_stat_callout); in rl_detach()
883 sc->suspended = 1; in rl_detach()
887 if (sc->rl_intrhand[0]) in rl_detach()
888 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); in rl_detach()
889 if (sc->rl_irq[0]) in rl_detach()
890 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]); in rl_detach()
891 if (sc->rl_res) in rl_detach()
892 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, in rl_detach()
893 sc->rl_res); in rl_detach()
900 mtx_destroy(&sc->rl_mtx); in rl_detach()
914 error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */ in rl_dma_alloc()
923 &sc->rl_parent_tag); in rl_dma_alloc()
925 device_printf(sc->rl_dev, in rl_dma_alloc()
930 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ in rl_dma_alloc()
939 &sc->rl_cdata.rl_rx_tag); in rl_dma_alloc()
941 device_printf(sc->rl_dev, in rl_dma_alloc()
946 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ in rl_dma_alloc()
955 &sc->rl_cdata.rl_tx_tag); in rl_dma_alloc()
957 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n"); in rl_dma_alloc()
964 error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag, in rl_dma_alloc()
965 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK | in rl_dma_alloc()
966 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap); in rl_dma_alloc()
968 device_printf(sc->rl_dev, in rl_dma_alloc()
973 error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag, in rl_dma_alloc()
974 sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf, in rl_dma_alloc()
978 device_printf(sc->rl_dev, in rl_dma_alloc()
982 sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr; in rl_dma_alloc()
986 sc->rl_cdata.rl_tx_chain[i] = NULL; in rl_dma_alloc()
987 sc->rl_cdata.rl_tx_dmamap[i] = NULL; in rl_dma_alloc()
988 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0, in rl_dma_alloc()
989 &sc->rl_cdata.rl_tx_dmamap[i]); in rl_dma_alloc()
991 device_printf(sc->rl_dev, in rl_dma_alloc()
998 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; in rl_dma_alloc()
999 sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE; in rl_dma_alloc()
1011 if (sc->rl_cdata.rl_rx_tag != NULL) { in rl_dma_free()
1012 if (sc->rl_cdata.rl_rx_buf_paddr != 0) in rl_dma_free()
1013 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag, in rl_dma_free()
1014 sc->rl_cdata.rl_rx_dmamap); in rl_dma_free()
1015 if (sc->rl_cdata.rl_rx_buf_ptr != NULL) in rl_dma_free()
1016 bus_dmamem_free(sc->rl_cdata.rl_rx_tag, in rl_dma_free()
1017 sc->rl_cdata.rl_rx_buf_ptr, in rl_dma_free()
1018 sc->rl_cdata.rl_rx_dmamap); in rl_dma_free()
1019 sc->rl_cdata.rl_rx_buf_ptr = NULL; in rl_dma_free()
1020 sc->rl_cdata.rl_rx_buf = NULL; in rl_dma_free()
1021 sc->rl_cdata.rl_rx_buf_paddr = 0; in rl_dma_free()
1022 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag); in rl_dma_free()
1023 sc->rl_cdata.rl_tx_tag = NULL; in rl_dma_free()
1027 if (sc->rl_cdata.rl_tx_tag != NULL) { in rl_dma_free()
1029 if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) { in rl_dma_free()
1031 sc->rl_cdata.rl_tx_tag, in rl_dma_free()
1032 sc->rl_cdata.rl_tx_dmamap[i]); in rl_dma_free()
1033 sc->rl_cdata.rl_tx_dmamap[i] = NULL; in rl_dma_free()
1036 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag); in rl_dma_free()
1037 sc->rl_cdata.rl_tx_tag = NULL; in rl_dma_free()
1040 if (sc->rl_parent_tag != NULL) { in rl_dma_free()
1041 bus_dma_tag_destroy(sc->rl_parent_tag); in rl_dma_free()
1042 sc->rl_parent_tag = NULL; in rl_dma_free()
1057 cd = &sc->rl_cdata; in rl_list_tx_init()
1059 cd->rl_tx_chain[i] = NULL; in rl_list_tx_init()
1064 sc->rl_cdata.cur_tx = 0; in rl_list_tx_init()
1065 sc->rl_cdata.last_tx = 0; in rl_list_tx_init()
1076 bzero(sc->rl_cdata.rl_rx_buf_ptr, in rl_list_rx_init()
1078 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap, in rl_list_rx_init()
1088 * You know there's something wrong with a PCI bus-master chip design
1095 * is preceded by a 32-bit RX status word which specifies the length
1097 * the status word) is also 32-bit aligned. The frame length is in the
1102 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1109 if_t ifp = sc->rl_ifp; in rl_rxeof()
1121 bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap, in rl_rxeof()
1130 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; in rl_rxeof()
1132 max_bytes = limit - cur_rx; in rl_rxeof()
1137 if (sc->rxcycles <= 0) in rl_rxeof()
1139 sc->rxcycles--; in rl_rxeof()
1142 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; in rl_rxeof()
1173 * the manual that explains how to do it) so we have in rl_rxeof()
1176 total_len -= ETHER_CRC_LEN; in rl_rxeof()
1185 rxbufpos = sc->rl_cdata.rl_rx_buf + in rl_rxeof()
1187 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) in rl_rxeof()
1188 rxbufpos = sc->rl_cdata.rl_rx_buf; in rl_rxeof()
1190 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; in rl_rxeof()
1195 m_copyback(m, wrap, total_len - wrap, in rl_rxeof()
1196 sc->rl_cdata.rl_rx_buf); in rl_rxeof()
1197 cur_rx = (total_len - wrap + ETHER_CRC_LEN); in rl_rxeof()
1204 /* Round up to 32-bit boundary. */ in rl_rxeof()
1206 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); in rl_rxeof()
1231 if_t ifp = sc->rl_ifp; in rl_txeof()
1250 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc), in rl_txeof()
1252 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc)); in rl_txeof()
1261 (sc->rl_txthresh < 2016)) in rl_txeof()
1262 sc->rl_txthresh += 32; in rl_txeof()
1271 oldthresh = sc->rl_txthresh; in rl_txeof()
1276 sc->rl_txthresh = oldthresh; in rl_txeof()
1279 RL_INC(sc->rl_cdata.last_tx); in rl_txeof()
1281 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); in rl_txeof()
1284 sc->rl_watchdog_timer = 0; in rl_txeof()
1303 * Tune the so-called twister registers of the RTL8139. These in rl_twister_update()
1308 switch (sc->rl_twister) in rl_twister_update()
1318 sc->rl_twister = FIND_ROW; in rl_twister_update()
1324 sc->rl_twister = DONE; in rl_twister_update()
1334 sc->rl_twist_row = 3; in rl_twister_update()
1336 sc->rl_twist_row = 2; in rl_twister_update()
1338 sc->rl_twist_row = 1; in rl_twister_update()
1340 sc->rl_twist_row = 0; in rl_twister_update()
1341 sc->rl_twist_col = 0; in rl_twister_update()
1342 sc->rl_twister = SET_PARAM; in rl_twister_update()
1345 if (sc->rl_twist_col == 0) in rl_twister_update()
1348 param[sc->rl_twist_row][sc->rl_twist_col]); in rl_twister_update()
1349 if (++sc->rl_twist_col == 4) { in rl_twister_update()
1350 if (sc->rl_twist_row == 3) in rl_twister_update()
1351 sc->rl_twister = RECHK_LONG; in rl_twister_update()
1353 sc->rl_twister = DONE; in rl_twister_update()
1363 sc->rl_twister = DONE; in rl_twister_update()
1366 sc->rl_twister = RETUNE; in rl_twister_update()
1375 sc->rl_twist_row--; in rl_twister_update()
1376 sc->rl_twist_col = 0; in rl_twister_update()
1377 sc->rl_twister = SET_PARAM; in rl_twister_update()
1396 * watchdog timeouts. This is a no-op in normal operations, but in rl_tick()
1405 mii = device_get_softc(sc->rl_miibus); in rl_tick()
1407 if ((sc->rl_flags & RL_FLAG_LINK) == 0) in rl_tick()
1408 rl_miibus_statchg(sc->rl_dev); in rl_tick()
1409 if (sc->rl_twister_enable) { in rl_tick()
1410 if (sc->rl_twister == DONE) in rl_tick()
1414 if (sc->rl_twister == DONE) in rl_tick()
1423 callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc); in rl_tick()
1448 sc->rxcycles = count; in rl_poll_locked()
1480 if_t ifp = sc->rl_ifp; in rl_intr()
1486 if (sc->suspended) in rl_intr()
1503 for (count = 16; count > 0; count--) { in rl_intr()
1549 * Hardware doesn't auto-pad, so we have to make sure in rl_encap()
1552 if (m->m_pkthdr.len < RL_MIN_FRAMELEN) in rl_encap()
1553 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len; in rl_encap()
1555 * The RealTek is brain damaged and wants longword-aligned in rl_encap()
1559 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 || in rl_encap()
1572 * Make security-conscious people happy: zero out the in rl_encap()
1577 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); in rl_encap()
1578 m->m_pkthdr.len += padlen; in rl_encap()
1579 m->m_len = m->m_pkthdr.len; in rl_encap()
1582 error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag, in rl_encap()
1593 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc), in rl_encap()
1622 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) in rl_start_locked()
1644 RL_TXTHRESH(sc->rl_txthresh) | in rl_start_locked()
1645 RL_CUR_TXMBUF(sc)->m_pkthdr.len); in rl_start_locked()
1647 RL_INC(sc->rl_cdata.cur_tx); in rl_start_locked()
1650 sc->rl_watchdog_timer = 5; in rl_start_locked()
1675 if_t ifp = sc->rl_ifp; in rl_init_locked()
1681 mii = device_get_softc(sc->rl_miibus); in rl_init_locked()
1692 if (sc->rl_twister_enable) { in rl_init_locked()
1699 sc->rl_twister = CHK_LINK; in rl_init_locked()
1709 bcopy(if_getlladdr(sc->rl_ifp), eaddr, ETHER_ADDR_LEN); in rl_init_locked()
1715 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr + in rl_init_locked()
1746 sc->rl_txthresh = RL_TX_THRESH_INIT; in rl_init_locked()
1754 sc->rl_flags &= ~RL_FLAG_LINK; in rl_init_locked()
1757 CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); in rl_init_locked()
1762 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc); in rl_init_locked()
1774 mii = device_get_softc(sc->rl_miibus); in rl_ifmedia_upd()
1792 mii = device_get_softc(sc->rl_miibus); in rl_ifmedia_sts()
1796 ifmr->ifm_active = mii->mii_media_active; in rl_ifmedia_sts()
1797 ifmr->ifm_status = mii->mii_media_status; in rl_ifmedia_sts()
1814 ((if_getflags(ifp) ^ sc->rl_if_flags) & in rl_ioctl()
1821 sc->rl_if_flags = if_getflags(ifp); in rl_ioctl()
1832 mii = device_get_softc(sc->rl_miibus); in rl_ioctl()
1833 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); in rl_ioctl()
1836 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); in rl_ioctl()
1838 if (ifr->ifr_reqcap & IFCAP_POLLING && in rl_ioctl()
1851 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && in rl_ioctl()
1886 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0) in rl_watchdog()
1889 device_printf(sc->rl_dev, "watchdog timeout\n"); in rl_watchdog()
1890 if_inc_counter(sc->rl_ifp, IFCOUNTER_OERRORS, 1); in rl_watchdog()
1894 if_setdrvflagbits(sc->rl_ifp, 0, IFF_DRV_RUNNING); in rl_watchdog()
1906 if_t ifp = sc->rl_ifp; in rl_stop()
1910 sc->rl_watchdog_timer = 0; in rl_stop()
1911 callout_stop(&sc->rl_stat_callout); in rl_stop()
1913 sc->rl_flags &= ~RL_FLAG_LINK; in rl_stop()
1924 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n"); in rl_stop()
1930 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { in rl_stop()
1931 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, in rl_stop()
1932 sc->rl_cdata.rl_tx_dmamap[i], in rl_stop()
1934 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, in rl_stop()
1935 sc->rl_cdata.rl_tx_dmamap[i]); in rl_stop()
1936 m_freem(sc->rl_cdata.rl_tx_chain[i]); in rl_stop()
1937 sc->rl_cdata.rl_tx_chain[i] = NULL; in rl_stop()
1959 sc->suspended = 1; in rl_suspend()
1967 * doesn't, re-enable busmastering, and restart the interface if
1979 ifp = sc->rl_ifp; in rl_resume()
1984 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) { in rl_resume()
1986 pmstat = pci_read_config(sc->rl_dev, in rl_resume()
1990 pci_write_config(sc->rl_dev, in rl_resume()
2004 sc->suspended = 0; in rl_resume()
2029 if_setflagbits(sc->rl_ifp, 0, IFF_UP); in rl_shutdown()
2046 ifp = sc->rl_ifp; in rl_setwol()
2049 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) in rl_setwol()
2056 v = CSR_READ_1(sc, sc->rl_cfg1); in rl_setwol()
2060 CSR_WRITE_1(sc, sc->rl_cfg1, v); in rl_setwol()
2062 v = CSR_READ_1(sc, sc->rl_cfg3); in rl_setwol()
2066 CSR_WRITE_1(sc, sc->rl_cfg3, v); in rl_setwol()
2068 v = CSR_READ_1(sc, sc->rl_cfg5); in rl_setwol()
2077 CSR_WRITE_1(sc, sc->rl_cfg5, v); in rl_setwol()
2083 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); in rl_setwol()
2087 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); in rl_setwol()
2096 ifp = sc->rl_ifp; in rl_clrwol()
2103 v = CSR_READ_1(sc, sc->rl_cfg3); in rl_clrwol()
2105 CSR_WRITE_1(sc, sc->rl_cfg3, v); in rl_clrwol()
2110 v = CSR_READ_1(sc, sc->rl_cfg5); in rl_clrwol()
2113 CSR_WRITE_1(sc, sc->rl_cfg5, v); in rl_clrwol()