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/linux/Documentation/devicetree/bindings/mailbox/
H A Dti,omap-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI OMAP2+ and K3 Mailbox devices
10 - Suman Anna <s-anna@ti.com>
13 The OMAP Mailbox hardware facilitates communication between different
14 processors using a queued mailbox interrupt mechanism. The IP block is
19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and
21 controller within a processor subsystem, and there can be more than one line
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H A Dmailbox.txt1 * Generic Mailbox Controller and client driver bindings
3 Generic binding to provide a way for Mailbox controller drivers to
4 assign appropriate mailbox channel to client drivers.
6 * Mailbox Controller
9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
13 mailbox: mailbox {
15 #mbox-cells = <1>;
19 * Mailbox Client
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
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H A Dhisilicon,hi3660-mailbox.txt1 Hisilicon Hi3660 Mailbox Controller
3 Hisilicon Hi3660 mailbox controller supports up to 32 channels. Messages
8 Controller
9 ----------
12 - compatible: : Shall be "hisilicon,hi3660-mbox"
13 - reg: : Offset and length of the device's register set
14 - #mbox-cells: : Must be 3
16 phandle : Label name of controller
21 - interrupts: : Contains the two IRQ lines for mailbox.
25 mailbox: mailbox@e896b000 {
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H A Daspeed,ast2700-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/aspeed,ast2700-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ASPEED AST2700 mailbox controller
10 - Jammy Huang <jammy_huang@aspeedtech.com>
14 other. The mailbox controller provides a way for these processors to send
15 messages to each other. It is a hardware-based inter-processor communication
19 The mailbox's tx/rx are independent, meaning that one processor can send a
25 The mailbox controller also supports interrupt generation, allowing
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H A Dxlnx,zynqmp-ipi-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx IPI(Inter Processor Interrupt) mailbox controller
10 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
14 +-------------------------------------+
15 | Xilinx ZynqMP IPI Controller |
16 +-------------------------------------+
17 +--------------------------------------------------+
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H A Dcix,sky1-mbox.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/cix,sky1-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cixtech mailbox controller
10 - Guomin Chen <Guomin.Chen@cixtech.com>
13 The Cixtech mailbox controller, used in the Cixtech Sky1 SoC,
18 Each Cixtech mailbox controller is unidirectional, so they are
19 typically used in pairs-one for receiving and one for transmitting.
21 Each Cixtech mailbox supports 11 channels with different transmission modes
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H A Daltera-mailbox.txt1 Altera Mailbox Driver
5 - compatible : "altr,mailbox-1.0".
6 - reg : physical base address of the mailbox and length of
8 - #mbox-cells: Common mailbox binding property to identify the number
9 of cells required for the mailbox specifier. Should be 1.
12 - interrupts : interrupt number. The interrupt specifier format
13 depends on the interrupt controller parent.
16 mbox_tx: mailbox@100 {
17 compatible = "altr,mailbox-1.0";
19 interrupt-parent = < &gic_0 >;
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H A Dhisilicon,hi6220-mailbox.txt1 Hisilicon Hi6220 Mailbox Driver
4 Hisilicon Hi6220 mailbox supports up to 32 channels. Each channel
9 Mailbox Device Node:
13 --------------------
14 - compatible: Shall be "hisilicon,hi6220-mbox"
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
20 of cells required for the mailbox specifier. Must be 3.
22 phandle: Label name of mailbox controller
27 mailbox driver uses it to acknowledge interrupt
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H A Dthead,th1520-mbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/thead,th1520-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-head TH1520 Mailbox Controller
10 The T-head mailbox controller enables communication and coordination between
12 through mailbox channels. It also allows one core to signal another processor
13 using interrupts via the Interrupt Controller Unit (ICU).
16 - Michal Wilczynski <m.wilczynski@samsung.com>
20 const: thead,th1520-mbox
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H A Dsprd-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/sprd-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Spreadtrum mailbox controller
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
17 - sprd,sc9860-mailbox
18 - sprd,sc9863a-mailbox
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H A Dmtk,adsp-mbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/mtk,adsp-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek ADSP mailbox
10 - Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
13 The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC
14 to communicate with ADSP by passing messages through two mailbox channels.
15 The MTK ADSP mailbox IPC also provides the ability for one processor to
21 - enum:
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H A Dqcom-ipcc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 The Inter-Processor Communication Controller (IPCC) is a centralized hardware
14 to route interrupts across various subsystems. It involves a three-level
18 a case, the client would be Modem (client-id is 2) and the signal would be
19 SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
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H A Dbrcm,bcm74110-mbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/brcm,bcm74110-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM74110 Mailbox
10 - Justin Chen <justin.chen@broadcom.com>
11 - Florian Fainelli <florian.fainelli@broadcom.com>
13 description: Broadcom mailbox hardware first introduced with 74110
18 - brcm,bcm74110-mbox
25 - description: RX doorbell and watermark interrupts
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/linux/drivers/mailbox/
H A Dbcm2835-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2013-2014 Lubomir Rintel
8 * - arch/arm/mach-bcm2708/vcio.c file written by Gray Girling that was
9 * obtained from branch "rpi-3.6.y" of git://github.com/raspberrypi/
11 * - drivers/mailbox/bcm2835-ipc.c by Lubomir Rintel at
12 * https://github.com/hackerspace/rpi-linux/blob/lr-raspberry-pi/drivers/
13 * mailbox/bcm2835-ipc.c
14 * - documentation available on the following web site:
15 * https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
19 #include <linux/dma-mapping.h>
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H A Dhi3660-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018 HiSilicon Limited.
3 // Copyright (c) 2017-2018 Linaro Limited.
18 #include "mailbox.h"
25 #define MBOX_BASE(mbox, ch) ((mbox)->base + ((ch) * 0x40))
48 * struct hi3660_chan_info - Hi3660 mailbox channel information
62 * struct hi3660_mbox - Hi3660 mailbox controller data
65 * @chan: Representation of channels in mailbox controller
67 * @controller: Representation of a communication channel controller
69 * Mailbox controller includes 32 channels and can allocate
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H A Dmailbox-xgene-slimpro.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * APM X-Gene SLIMpro MailBox Driver
18 #define MBOX_CON_NAME "slimpro-mbox"
35 * X-Gene SlimPRO mailbox channel information
38 * @chan: Pointer to mailbox communication channel
52 * X-Gene SlimPRO Mailbox controller data
54 * X-Gene SlimPRO Mailbox controller has 8 communication channels.
57 * @mb_ctrl: Representation of the communication channel controller
58 * @mc: Array of SlimPRO mailbox channels of the controller
59 * @chans: Array of mailbox communication channels
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H A Domap-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
3 * OMAP mailbox driver
5 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
6 * Copyright (C) 2013-2021 Texas Instruments Incorporated - https://www.ti.com
9 * Suman Anna <s-anna@ti.com>
26 #include "mailbox.h"
97 return __raw_readl(mdev->mbox_base + ofs); in mbox_read_reg()
103 __raw_writel(val, mdev->mbox_base + ofs); in mbox_write_reg()
106 /* Mailbox FIFO handle functions */
109 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; in mbox_fifo_read()
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H A Darmada-37xx-rwtm-mailbox.c1 // SPDX-License-Identifier: GPL-2.0+
3 * rWTM BIU Mailbox driver for Armada 37xx
16 #include <linux/armada-37xx-rwtm-mailbox.h>
18 #define DRIVER_NAME "armada-37xx-rwtm-mailbox"
20 /* relative to rWTM BIU Mailbox Registers */
38 struct mbox_controller controller; member
45 struct a37xx_mbox *mbox = chan->con_priv; in a37xx_mbox_receive()
49 rx_msg.retval = readl(mbox->base + RWTM_MBOX_RETURN_STATUS); in a37xx_mbox_receive()
51 rx_msg.status[i] = readl(mbox->base + RWTM_MBOX_STATUS(i)); in a37xx_mbox_receive()
59 struct a37xx_mbox *mbox = chan->con_priv; in a37xx_mbox_irq_handler()
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H A Dmailbox-altera.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright Altera Corporation (C) 2013-2014. All rights reserved
15 #define DRIVER_NAME "altera-mailbox"
40 bool is_sender; /* 1-sender, 0-receiver */
45 struct mbox_controller controller; member
47 /* If the controller supports only RX polling mode */
54 if (!chan || !chan->con_priv) in mbox_chan_to_altera_mbox()
57 return (struct altera_mbox *)chan->con_priv; in mbox_chan_to_altera_mbox()
64 status = readl_relaxed(mbox->mbox_base + MAILBOX_STS_REG); in altera_mbox_full()
72 status = readl_relaxed(mbox->mbox_base + MAILBOX_STS_REG); in altera_mbox_pending()
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H A Dhi6220-mailbox.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hisilicon's Hi6220 mailbox driver
26 /* Mailbox message length: 8 words */
29 /* Mailbox Registers */
57 * - direction: tx or rx
58 * - dst irq: peer core's irq number
59 * - ack irq: local irq number
60 * - slot number
79 /* region for mailbox */
87 struct mbox_controller controller; member
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/linux/drivers/scsi/smartpqi/
H A Dsmartpqi_sis.c1 // SPDX-License-Identifier: GPL-2.0
3 * driver for Microchip PQI-based storage controllers
4 * Copyright (c) 2019-2023 Microchip Technology Inc. and its subsidiaries
5 * Copyright (c) 2016-2018 Microsemi Corporation
6 * Copyright (c) 2016 PMC-Sierra, Inc.
110 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_wait_for_ctrl_ready_with_timeout()
113 dev_err(&ctrl_info->pci_dev->dev, in sis_wait_for_ctrl_ready_with_timeout()
114 "controller is offline: status code 0x%x\n", in sis_wait_for_ctrl_ready_with_timeout()
116 &ctrl_info->registers->sis_mailbox[7])); in sis_wait_for_ctrl_ready_with_timeout()
117 return -ENODEV; in sis_wait_for_ctrl_ready_with_timeout()
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/linux/include/linux/platform_data/
H A Dwilco-ec.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * ChromeOS Wilco Embedded Controller
14 /* Message flags for using the mailbox() interface */
25 * struct wilco_ec_device - Wilco Embedded Controller handle.
27 * @mailbox_lock: Mutex to ensure one mailbox command at a time.
28 * @io_command: I/O port for mailbox command. Provided by ACPI.
29 * @io_data: I/O port for mailbox data. Provided by ACPI.
30 * @io_packet: I/O port for mailbox packet data. Provided by ACPI.
34 * @debugfs_pdev: The child platform_device used by the debugfs sub-driver.
35 * @rtc_pdev: The child platform_device used by the RTC sub-driver.
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/linux/Documentation/networking/device_drivers/can/freescale/
H A Dflexcan.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 Flexcan CAN Controller driver
7 Authors: Marc Kleine-Budde <mkl@pengutronix.de>,
15 - FIFO
16 - mailbox
19 and i.MX53 SOCs) only receive RTR frames if the controller is
20 configured for RX-FIFO mode.
23 while the mailbox mode uses a software FIFO with a depth of up to 62
24 CAN frames. With the help of the bigger buffer, the mailbox mode
30 With the "rx-rtr" private flag the ability to receive RTR frames can
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/linux/Documentation/networking/device_drivers/ethernet/marvell/
H A Docteon_ep.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - `Overview`_
14 - `Supported Devices`_
15 - `Interface Control`_
25 * Network controller: Cavium, Inc. Device b100
26 * Network controller: Cavium, Inc. Device b200
27 * Network controller: Cavium, Inc. Device b400
28 * Network controller: Cavium, Inc. Device b900
29 * Network controller: Cavium, Inc. Device ba00
30 * Network controller: Cavium, Inc. Device bc00
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-lsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 lsio_bus_clk: clock-lsio-bus {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <100000000>;
14 clock-output-names = "lsio_bus_clk";
18 compatible = "simple-bus";
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