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/linux/Documentation/devicetree/bindings/net/
H A Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
25 - st,stm32mp13-dwmac
26 - st,stm32mp25-dwmac
[all …]
H A Dnxp,dwmac-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clark Wang <xiaoning.wang@nxp.com>
11 - Shawn Guo <shawnguo@kernel.org>
12 - NXP Linux Team <linux-imx@nxp.com>
20 - nxp,imx8mp-dwmac-eqos
21 - nxp,imx8dxl-dwmac-eqos
22 - nxp,imx93-dwmac-eqos
[all …]
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
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H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
[all …]
H A Dingenic,mac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ingenic,mac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MAC in Ingenic SoCs
10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
18 - ingenic,jz4775-mac
19 - ingenic,x1000-mac
20 - ingenic,x1600-mac
21 - ingenic,x1830-mac
[all …]
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
23 transformer. This device interfaces directly to the MAC layer through the
34 nvmem-cells:
40 nvmem-cell-names:
[all …]
H A Dsti-dwmac.txt10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - resets : phandle pointing to the system reset controller with correct
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
21 MAC can generate it.
22 - st,tx-retime-src: This specifies which clk is wired up to the mac for
23 retimeing tx lines. This is totally board dependent and can take one of the
26 - sti-ethclk: this is the phy clock.
[all …]
H A Dtesla,fsd-ethqos.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/tesla,fsd-ethqos.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Swathi K S <swathi.ks@samsung.com>
16 - $ref: snps,dwmac.yaml#
20 const: tesla,fsd-ethqos
28 interrupt-names:
30 - const: macirq
35 - description: PTP clock
[all …]
/linux/drivers/net/ethernet/faraday/
H A Dftgmac100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
11 #include <linux/clk.h>
13 #include <linux/dma-mapping.h>
49 /* Min number of tx ring entries before stopping queue */
55 /* For NC-SI to register a fixed-link phy device */
77 /* Tx ring */
101 struct clk *clk; member
104 struct clk *rclk;
[all …]
/linux/arch/arm64/boot/dts/st/
H A Dstm32mp253.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&CPU_PD1>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 CPU_PD1: power-domain-cpu1 {
28 #power-domain-cells = <0>;
[all …]
H A Dstm32mp233.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&cpu1_pd>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 cpu1_pd: power-domain-cpu1 {
28 #power-domain-cells = <0>;
[all …]
/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
27 Currently, this network device driver is for all STi embedded MAC/GMAC
32 DesignWare(R) Cores Ethernet MAC 10/100/1000 Universal version 3.70a
[all …]
/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_define.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define MAX_NETDEV_NUM 2 /* Maximum # of net-device */
21 #define MAC_INT_TX_SOC_PAUSE_ON BIT(15) /* Soc Port TX Pause On */
29 #define MAC_INT_TX_DONE_L BIT(3) /* TX Low Priority Done */
30 #define MAC_INT_TX_DONE_H BIT(2) /* TX High Priority Done */
31 #define MAC_INT_TX_DES_ERR BIT(1) /* TX Descriptor Error */
63 /* Wt mac ad0 */
77 /* W mac 15_0 bus */
80 /* W mac 47_16 bus */
154 /* MAC force mode */
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
16 #include <linux/clk.h>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
35 static int mtk_msg_level = -1;
37 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
291 __raw_writel(val, eth->base + reg); in mtk_w32()
296 return __raw_readl(eth->base + reg); in mtk_r32()
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dbcm63xx_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 /* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
29 * hardware maximum rx/tx packet size including FCS, max mtu is
199 /* mac irq, rx_dma irq, tx_dma irq */
204 /* hw view of rx & tx dma ring */
208 /* allocated size (in bytes) for rx & tx dma ring */
253 /* dma channel id for tx */
256 /* number of dma desc in tx ring */
265 /* number of available descriptor for tx */
268 /* next tx descriptor avaiable */
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-s32.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2019-2024 NXP
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
37 struct clk *tx_clk;
38 struct clk *rx_clk;
43 writel(PHY_INTF_SEL_RGMII, gmac->ctrl_sts); in s32_gmac_write_phy_intf_select()
45 dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode)); in s32_gmac_write_phy_intf_select()
55 /* Set initial TX interface clock */ in s32_gmac_init()
56 ret = clk_prepare_enable(gmac->tx_clk); in s32_gmac_init()
[all …]
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/linux/drivers/net/ethernet/actions/
H A Dowl-emac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Actions Semi Owl SoCs Ethernet MAC driver
10 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
19 #include "owl-emac.h"
27 return readl(priv->base + reg); in owl_emac_reg_read()
32 writel(data, priv->base + reg); in owl_emac_reg_write()
63 return priv->netdev->dev.parent; in owl_emac_get_dev()
84 * unexpected side effect (MAC hardware bug?!) where some bits in the in owl_emac_irq_disable()
129 return dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); in owl_emac_dma_map_tx()
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
[all …]
/linux/drivers/net/ethernet/arc/
H A Demac_main.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
29 * arc_emac_tx_avail - Return the number of available slots in the tx ring.
32 * returns: the number of slots available for transmission in tx the ring.
36 return (priv->txbd_dirty + TX_BD_NUM - priv->txbd_curr - 1) % TX_BD_NUM; in arc_emac_tx_avail()
40 * arc_emac_adjust_link - Adjust the PHY link duplex.
49 struct phy_device *phy_dev = ndev->phydev; in arc_emac_adjust_link()
52 if (priv->link != phy_dev->link) { in arc_emac_adjust_link()
53 priv->link = phy_dev->link; in arc_emac_adjust_link()
57 if (priv->speed != phy_dev->speed) { in arc_emac_adjust_link()
[all …]
H A Demac.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
12 #include <linux/dma-mapping.h>
15 #include <linux/clk.h>
31 #define TXRN_MASK (1 << 3) /* TX enable */
34 #define ENFL_MASK (1 << 10) /* Enable Full-duplex */
38 #define OWN_MASK (1 << 31) /* 0-CPU or 1-EMAC owns buffer */
52 /* ARC EMAC register set combines entries for MAC and MDIO */
77 * struct arc_emac_bd - EMAC buffer descriptor (BD).
80 * @data: 32-bit byte addressable pointer to the packet data.
[all …]
/linux/drivers/net/ethernet/atheros/
H A Dag71xx.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Atheros AR71xx built-in ethernet mac driver
11 * David Bauer <mail@david-bauer.net>
14 * Hauke Mehrtens <hauke@hauke-m.de>
15 * Johann Neuhauser <johann@it-neuhauser.de>
17 * Jo-Philipp Wich <jo@mein.io>
39 #include <linux/clk.h>
43 /* For our NAPI weight bigger does *NOT* mean better - it means more
44 * D-cache misses and lots more wasted cycles than we'll ever
71 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
[all …]
/linux/include/linux/
H A Dstmmac.h1 /* SPDX-License-Identifier: GPL-2.0-only */
48 /* RX/TX Queue Mode */
81 struct clk;
192 /* MAC ---
[all...]
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28-var4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
12 /dts-v1/;
13 #include "fsl-ls1028a-kontron-sl28.dts"
14 #include <dt-bindings/net/qca-ar803x.h>
17 model = "Kontron SMARC-sAL28 (Dual PHY)";
18 compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
22 phy1: ethernet-phy@4 {
24 eee-broken-1000t;
25 eee-broken-100tx;
[all …]

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