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/linux/drivers/media/platform/renesas/vsp1/
H A Dvsp1_lut.c28 static inline void vsp1_lut_write(struct vsp1_lut *lut, in vsp1_lut_write() argument
40 static int lut_set_table(struct vsp1_lut *lut, struct v4l2_ctrl *ctrl) in lut_set_table() argument
45 dlb = vsp1_dl_body_get(lut->pool); in lut_set_table()
53 spin_lock_irq(&lut->lock); in lut_set_table()
54 swap(lut->lut, dlb); in lut_set_table()
55 spin_unlock_irq(&lut->lock); in lut_set_table()
63 struct vsp1_lut *lut = in lut_s_ctrl() local
68 lut_set_table(lut, ctrl); in lut_s_ctrl()
154 struct vsp1_lut *lut = to_lut(&entity->subdev); in lut_configure_stream() local
156 vsp1_lut_write(lut, dlb, VI6_LUT_CTRL, VI6_LUT_CTRL_EN); in lut_configure_stream()
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_color.c38 * - Input gamma LUT (de-normalized)
40 * - Surface degamma LUT (normalized)
42 * - Surface regamma LUT (normalized)
51 * The input gamma LUT block isn't really applicable here since it operates
64 * respective property is set to NULL. A linear DGM/RGM LUT should also
108 * degamma TF, shaper TF (before 3D LUT), and blend(dpp.ogam) TF and
330 * __extract_blob_lut - Extracts the DRM lut and lut size from a blob.
332 * @size: lut size
335 * DRM LUT or NULL
345 * __is_lut_linear - check if the given lut is a linear mapping of values
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_disp_gamma.c35 /* For 10 bit LUT layout, R/G/B are in the same register */
40 /* For 12 bit LUT layout, R/G are in LUT, B is in LUT1 */
90 static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut_size) in mtk_gamma_lut_is_descending() argument
95 first = lut[0].red + lut[0].green + lut[0].blue; in mtk_gamma_lut_is_descending()
96 last = lut[last_entry].red + lut[last_entry].green + lut[last_entry].blue; in mtk_gamma_lut_is_descending()
103 * always support (by HW) both 12-bits and 10-bits LUT but, on those, we
107 * - SoC HW support 9/10-bits LUT only
109 * - 10-bits LUT supported
110 * - 9-bits LUT not supported
111 * - SoC HW support both 10/12bits LUT
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H A Dmtk_disp_aal.c82 * mtk_aal_gamma_get_lut_size() - Get gamma LUT size for AAL
85 * Return: 0 if gamma control not supported in AAL or gamma LUT size
99 struct drm_color_lut *lut; in mtk_aal_gamma_set() local
107 /* Also, if there's no gamma lut there's nothing to do here. */ in mtk_aal_gamma_set()
111 lut = (struct drm_color_lut *)state->gamma_lut->data; in mtk_aal_gamma_set()
114 .red = drm_color_lut_extract(lut[i].red, DISP_AAL_LUT_BITS), in mtk_aal_gamma_set()
115 .green = drm_color_lut_extract(lut[i].green, DISP_AAL_LUT_BITS), in mtk_aal_gamma_set()
116 .blue = drm_color_lut_extract(lut[i].blue, DISP_AAL_LUT_BITS) in mtk_aal_gamma_set()
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_cmm.c27 * @lut: 1D-LUT state
28 * @lut.enabled: 1D-LUT enabled flag
32 } lut; member
46 * rcar_cmm_lut_write() - Scale the DRM LUT table entries to hardware precision
49 * @drm_lut: Pointer to the DRM LUT table
71 * disabling and programming of the 1-D LUT unit is supported.
78 * TODO: Add support for LUT double buffer operations to avoid updating the
79 * LUT table entries while a frame is being displayed.
86 /* Disable LUT if no table is provided. */ in rcar_cmm_setup()
87 if (!config->lut.table) { in rcar_cmm_setup()
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H A Drcar_cmm.h19 * @lut: 1D-LUT configuration
20 * @lut.table: 1D-LUT table entries. Disable LUT operations when NULL
25 } lut; member
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_util.h98 * @ lut_flag: scaler LUT update flags
99 * 0x1 swap LUT bank
100 * 0x2 update 2D filter LUT
101 * 0x4 update y circular filter LUT
102 * 0x8 update uv circular filter LUT
103 * 0x10 update y separable filter LUT
104 * 0x20 update uv separable filter LUT
105 * @ dir_lut_idx: 2D filter LUT index
106 * @ y_rgb_cir_lut_idx: y circular filter LUT index
107 * @ uv_cir_lut_idx: uv circular filter LUT index
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H A Ddpu_hw_catalog.c591 {.fl = 4, .lut = 0x1b},
592 {.fl = 5, .lut = 0x5b},
593 {.fl = 6, .lut = 0x15b},
594 {.fl = 7, .lut = 0x55b},
595 {.fl = 8, .lut = 0x155b},
596 {.fl = 9, .lut = 0x555b},
597 {.fl = 10, .lut = 0x1555b},
598 {.fl = 11, .lut = 0x5555b},
599 {.fl = 12, .lut = 0x15555b},
600 {.fl = 0, .lut = 0x55555b}
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H A Ddpu_hw_util.c119 u32 *lut[QSEED3_FILTERS] = {NULL, NULL, NULL, NULL, NULL}; in _dpu_hw_setup_scaler3_lut() local
131 lut[0] = scaler3_cfg->dir_lut; in _dpu_hw_setup_scaler3_lut()
137 lut[1] = scaler3_cfg->cir_lut + in _dpu_hw_setup_scaler3_lut()
144 lut[2] = scaler3_cfg->cir_lut + in _dpu_hw_setup_scaler3_lut()
151 lut[3] = scaler3_cfg->sep_lut + in _dpu_hw_setup_scaler3_lut()
158 lut[4] = scaler3_cfg->sep_lut + in _dpu_hw_setup_scaler3_lut()
165 if (!lut[filter]) in _dpu_hw_setup_scaler3_lut()
175 (lut[filter])[lut_offset++]); in _dpu_hw_setup_scaler3_lut()
194 u32 *lut[QSEED3LITE_FILTERS] = {NULL, NULL}; in _dpu_hw_setup_scaler3lite_lut() local
206 lut[0] = scaler3_cfg->sep_lut + in _dpu_hw_setup_scaler3lite_lut()
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/linux/drivers/video/fbdev/
H A Dmacfb.c58 unsigned char lut; member
64 unsigned char lut; member
73 unsigned char lut; member
79 unsigned char lut; /* OFFSET: 0x10 */ member
101 unsigned char lut; member
106 unsigned char lut; /* TFBClutWDataReg, offset 0x90018 */ member
114 unsigned char lut; member
167 &dafb_cmap_regs->lut); in dafb_setpalette()
170 &dafb_cmap_regs->lut); in dafb_setpalette()
173 &dafb_cmap_regs->lut); in dafb_setpalette()
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/linux/include/drm/
H A Ddrm_color_mgmt.h34 * drm_color_lut_extract - clamp and round LUT entries
36 * @bit_precision: number of bits the hw LUT supports
38 * Extract a degamma/gamma LUT value provided by user (in the form of
64 * drm_color_lut_size - calculate the number of entries in the LUT
65 * @blob: blob containing the LUT
68 * The number of entries in the color LUT stored in @blob.
95 * enum drm_color_lut_tests - hw-specific LUT tests to perform
98 * determine which tests to apply to a userspace-provided LUT.
104 * Checks whether the entries of a LUT all have equal values for the
106 * accepts a single value per LUT entry and assumes that value applies
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_mode.h348 /* @plane_degamma_lut_property: Plane property to set a degamma LUT to
354 * size of degamma LUT as supported by the driver (read-only).
369 * @shaper_lut_property: Plane property to set pre-blending shaper LUT
370 * that converts color content before 3D LUT. If
372 * combine the user LUT values with pre-defined TF into the LUT
378 * pre-blending shaper LUT as supported by the driver (read-only).
383 * transfer function for pre-blending shaper (before applying 3D LUT)
384 * with or without LUT. There is no shaper ROM, but we can use AMD
385 * color modules to program LUT parameters from predefined TF (or
386 * from a combination of pre-defined TF and the custom 1D LUT).
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/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dlut.c22 #include "lut.h"
32 nv50_lut_load(struct nv50_lut *lut, int buffer, struct drm_property_blob *blob, in nv50_lut_load() argument
36 void __iomem *mem = lut->mem[buffer].object.map.ptr; in nv50_lut_load()
37 const u32 addr = lut->mem[buffer].addr; in nv50_lut_load()
59 nv50_lut_fini(struct nv50_lut *lut) in nv50_lut_fini() argument
62 for (i = 0; i < ARRAY_SIZE(lut->mem); i++) in nv50_lut_fini()
63 nvif_mem_dtor(&lut->mem[i]); in nv50_lut_fini()
68 struct nv50_lut *lut) in nv50_lut_init() argument
72 for (i = 0; i < ARRAY_SIZE(lut->mem); i++) { in nv50_lut_init()
74 size * 8, &lut->mem[i]); in nv50_lut_init()
/linux/drivers/staging/media/atomisp/pci/isp/kernels/bnlm/
H A Dia_css_bnlm.host.c39 * lut : bnlm_lut struct containing encoded vmem parameters look-up table
40 * lut_thr : array containing threshold values for lut
45 bnlm_lut_encode(struct bnlm_lut *lut, const int32_t *lut_thr, in bnlm_lut_encode() argument
54 * Min size of the LUT is 2 entries. in bnlm_lut_encode()
56 * Max size of the LUT is 16 entries, so that the LUT can fit into a in bnlm_lut_encode()
59 * vector. If the LUT size is less than 16, then remaining elements are in bnlm_lut_encode()
71 lut->thr[0][i] = 0; in bnlm_lut_encode()
72 lut->val[0][i] = 0; in bnlm_lut_encode()
77 lut->thr[0][i] = lut_thr[i]; in bnlm_lut_encode()
78 lut->val[0][i] = lut_val[i]; in bnlm_lut_encode()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_color.c177 static bool lut_is_legacy(const struct drm_property_blob *lut) in lut_is_legacy() argument
179 return lut && drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; in lut_is_legacy()
516 * On GLK both pipe CSC and degamma LUT are controlled in ilk_assign_csc()
518 * LUT is needed but CSC is not we need to load an in ilk_assign_csc()
786 /* convert hw value with given bit_precision to lut property val */
1152 struct drm_color_lut *lut; in create_linear_lut() local
1156 sizeof(lut[0]) * lut_size, in create_linear_lut()
1161 lut = blob->data; in create_linear_lut()
1166 lut[i].red = val; in create_linear_lut()
1167 lut[i].green = val; in create_linear_lut()
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/linux/drivers/gpu/drm/
H A Ddrm_color_mgmt.c42 * Blob property to set the degamma lookup table (LUT) mapping pixel data
45 * Hardware might choose not to use the full precision of the LUT elements
46 * nor use all the elements of the LUT (for example the hardware might
47 * choose to interpolate between LUT[0] and LUT[4]).
57 * hardware). If drivers support multiple LUT sizes then they should
63 * pixel data after the lookup through the degamma LUT and before the
64 * lookup through the gamma LUT. The data is interpreted as a struct
73 * Blob property to set the gamma lookup table (LUT) mapping pixel data
76 * Hardware might choose not to use the full precision of the LUT elements
77 * nor use all the elements of the LUT (for example the hardware might
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/linux/drivers/gpio/
H A Dgpio-adp5520.c19 unsigned char lut[ADP5520_MAXGPIOS]; member
40 return !!(reg_val & dev->lut[off]); in adp5520_gpio_get_value()
50 adp5520_set_bits(dev->master, ADP5520_GPIO_OUT, dev->lut[off]); in adp5520_gpio_set_value()
52 adp5520_clr_bits(dev->master, ADP5520_GPIO_OUT, dev->lut[off]); in adp5520_gpio_set_value()
63 dev->lut[off]); in adp5520_gpio_direction_input()
77 dev->lut[off]); in adp5520_gpio_direction_output()
80 dev->lut[off]); in adp5520_gpio_direction_output()
83 dev->lut[off]); in adp5520_gpio_direction_output()
114 dev->lut[gpios++] = 1 << i; in adp5520_gpio_probe()
/linux/drivers/net/ethernet/aquantia/atlantic/macsec/
H A DMSS_Ingress_registers.h50 * (IGPRCTLF) LUT
51 * 0x1 : Ingress Pre-Security Classification LUT (IGPRC)
52 * 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT
53 * 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT
54 * 0x4 : Ingress Post-Security Classification LUT
57 * (IGPOCTLF) LUT
H A DMSS_Egress_registers.h51 /* 0x0 : Egress MAC Control FIlter (CTLF) LUT
52 * 0x1 : Egress Classification LUT
53 * 0x2 : Egress SC/SA LUT
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_surface.c248 struct dc_3dlut *lut = container_of(kref, struct dc_3dlut, refcount); in dc_3dlut_func_free() local
250 kvfree(lut); in dc_3dlut_func_free()
255 struct dc_3dlut *lut = kvzalloc(sizeof(*lut), GFP_KERNEL); in dc_create_3dlut_func() local
257 if (lut == NULL) in dc_create_3dlut_func()
260 kref_init(&lut->refcount); in dc_create_3dlut_func()
261 lut->state.raw = 0; in dc_create_3dlut_func()
263 return lut; in dc_create_3dlut_func()
270 void dc_3dlut_func_release(struct dc_3dlut *lut) in dc_3dlut_func_release() argument
272 kref_put(&lut->refcount, dc_3dlut_func_free); in dc_3dlut_func_release()
275 void dc_3dlut_func_retain(struct dc_3dlut *lut) in dc_3dlut_func_retain() argument
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/linux/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
H A Dinput_formatter_local.h41 * The switch LUT's coding defines a sink for each
46 * LUT[0,1] channel=0, format type {0,1,...31}
47 * LUT[2,3] channel=1, format type {0,1,...31}
48 * LUT[4,5] channel=2, format type {0,1,...31}
49 * LUT[6,7] channel=3, format type {0,1,...31}
58 * a channel to a sink. At that point the LUT's belonging to
H A Dgdc.c65 * Input LUT format:
68 * Output LUT format (interleaved):
73 * to program gdc LUT registers. This makes it difficult to do piecemeal
77 * gdc LUT registers.
/linux/drivers/clk/rockchip/
H A Dsoftrst.c15 const int *lut; member
31 if (softrst->lut) in rockchip_softrst_assert()
32 id = softrst->lut[id]; in rockchip_softrst_assert()
63 if (softrst->lut) in rockchip_softrst_deassert()
64 id = softrst->lut[id]; in rockchip_softrst_deassert()
106 softrst->lut = lookup_table; in rockchip_register_softrst_lut()
/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_common.c319 * @lut: pointer to the lut buffer provided by the caller
320 * @lut_size: size of the lut buffer
327 u8 *lut, u16 lut_size, in iavf_aq_get_set_rss_lut() argument
360 status = iavf_asq_send_command(hw, &desc, lut, lut_size, NULL); in iavf_aq_get_set_rss_lut()
370 * @lut: pointer to the lut buffer provided by the caller
371 * @lut_size: size of the lut buffer
376 bool pf_lut, u8 *lut, u16 lut_size) in iavf_aq_set_rss_lut() argument
378 return iavf_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); in iavf_aq_set_rss_lut()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dmpc.h33 * 3D LUT.
689 * Power on/off memory LUT for given MPCC.
690 * Powering on enables LUT to be updated.
811 * - [in] params - curve parameters for the LUT configuration
814 …* bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled…
833 …* bool - wheter shaper was set (set with given parameters) or not (params is NULL and LUT is disab…
863 * - [in] params - tetrahedral parameters for the LUT configuration
866 …* bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled…
957 * Update 3D LUT fast load select.
973 …* Get 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow poin…
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