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/linux/Documentation/devicetree/bindings/mfd/
H A Daspeed-lpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Aspeed Low Pin Count (LPC) Bus Controller
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
17 primary use case of the Aspeed LPC controller is as a slave on the bus
21 The LPC controller is represented as a multi-function device to account for the
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/linux/Documentation/devicetree/bindings/ipmi/
H A Daspeed,ast2400-kcs-bmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
13 The Aspeed BMC SoCs typically use the Keyboard-Controller-Style (KCS)
14 interfaces on the LPC bus for in-band IPMI communication with their host.
19 - description: Channel ID derived from reg
22 - aspeed,ast2400-kcs-bmc-v2
23 - aspeed,ast2500-kcs-bmc-v2
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H A Dnpcm7xx-kcs-bmc.txt5 used to perform in-band IPMI communication with their host.
8 - compatible : should be one of
9 "nuvoton,npcm750-kcs-bmc"
10 "nuvoton,npcm845-kcs-bmc", "nuvoton,npcm750-kcs-bmc"
11 - interrupts : interrupt generated by the controller
12 - kcs_chan : The KCS channel number in the controller
17 compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
19 reg-io-width = <1>;
21 #address-cells = <1>;
22 #size-cells = <1>;
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/linux/Documentation/devicetree/bindings/serial/
H A D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
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/linux/Documentation/devicetree/bindings/rtc/
H A Drtc-st-lpc.txt1 STMicroelectronics Low Power Controller (LPC) - RTC
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
8 [See: ../timer/st,stih407-lpc for Clocksource options]
12 - compatible : Must be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
23 lpc@fde05000 {
24 compatible = "st,stih407-lpc";
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/linux/Documentation/devicetree/bindings/timer/
H A Dst,stih407-lpc1 STMicroelectronics Low Power Controller (LPC) - Clocksource
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
8 [See: ../rtc/rtc-st-lpc.txt for RTC options]
12 - compatible : Must be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
23 lpc@fde05000 {
24 compatible = "st,stih407-lpc";
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/linux/Documentation/devicetree/bindings/watchdog/
H A Dst_lpc_wdt.txt1 STMicroelectronics Low Power Controller (LPC) - Watchdog
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
7 [See: ../rtc/rtc-st-lpc.txt for RTC options]
8 [See: ../timer/st,stih407-lpc for Clocksource options]
12 - compatible : Should be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
24 - st,syscfg : Phandle to syscfg node used to enable watchdog and configure
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/linux/Documentation/devicetree/bindings/net/
H A Dlpc-eth.txt4 - compatible: Should be "nxp,lpc-eth"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain ethernet controller interrupt
9 - phy-mode: See ethernet.txt file in the same directory. If the property is
11 - use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering
14 - mdio : specifies the mdio bus, used as a container for phy nodes according to
21 compatible = "nxp,lpc-eth";
23 interrupt-parent = <&mic>;
24 interrupts = <29 0>;
26 phy-mode = "rmii";
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/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-g4.dtsi1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&vic>;
35 #address-cells = <1>;
36 #size-cells = <0>;
39 compatible = "arm,arm926ej-s";
51 compatible = "simple-bus";
52 #address-cells = <1>;
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H A Daspeed-g6.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
6 #include <dt-bindings/clock/ast2600-clock.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49 enable-method = "aspeed,ast2600-smp";
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H A Daspeed-g5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&vic>;
36 #address-cells = <1>;
37 #size-cells = <0>;
40 compatible = "arm,arm1176jzf-s";
52 compatible = "simple-bus";
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H A Daspeed-bmc-amd-ethanolx.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
6 #include "aspeed-g5.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
12 compatible = "amd,ethanolx-bmc", "aspeed,ast2500";
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
26 compatible = "shared-dma-pool";
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H A Daspeed-bmc-tyan-s8036.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g5.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "tyan,s8036-bmc", "aspeed,ast2500";
13 stdout-path = &uart5;
22 reserved-memory {
23 #address-cells = <1>;
24 #size-cells = <1>;
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H A Daspeed-bmc-amd-daytonax.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "aspeed-g5.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "amd,daytonax-bmc", "aspeed,ast2500";
16 reserved-memory {
17 #address-cells = <1>;
18 #size-cells = <1>;
24 compatible = "shared-dma-pool";
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H A Daspeed-bmc-asrock-spc621d8hm3.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g5.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
6 #include <dt-bindings/i2c/i2c.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/leds/common.h>
12 compatible = "asrock,spc621d8hm3-bmc", "aspeed,ast2500";
22 stdout-path = &uart5;
30 compatible = "gpio-leds";
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/linux/arch/arm/boot/dts/st/
H A Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
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/linux/drivers/tty/serial/8250/
H A D8250_aspeed_vuart.c1 // SPDX-License-Identifier: GPL-2.0+
61 * to the host on the Host <-> BMC LPC bus. It could be different on a
67 return readb(vuart->port->port.membase + reg); in aspeed_vuart_readb()
72 writeb(val, vuart->port->port.membase + reg); in aspeed_vuart_writeb()
90 return -EINVAL; in aspeed_vuart_set_lpc_address()
134 return -EINVAL; in aspeed_vuart_set_sirq()
250 struct aspeed_vuart *vuart = uart_8250_port->port.private_data; in aspeed_vuart_startup()
265 struct aspeed_vuart *vuart = uart_8250_port->port.private_data; in aspeed_vuart_shutdown()
278 lockdep_assert_held_once(&up->port.lock); in __aspeed_vuart_set_throttle()
280 up->ier &= ~irqs; in __aspeed_vuart_set_throttle()
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/linux/drivers/char/
H A Ddtlk.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* -*- linux-c -*-
3 * dtlk.c - DoubleTalk PC driver for Linux
8 * 2000-03-18 Jim Van Zandt: Fix polling.
20 The DoubleTalk PC contains four voice synthesizers: text-to-speech
21 (TTS), linear predictive coding (LPC), PCM/ADPCM, and CVSD. It
22 also has a tone generator. Output data for LPC are written to the
23 LPC port, and output data for the other modes are written to the
29 of the speech) are read from the LPC port. Not all models of the
30 DoubleTalk PC implement index markers. Both the TTS and LPC ports
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/linux/drivers/char/ipmi/
H A Dkcs_bmc_aspeed.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2018, Intel Corporation.
6 #define pr_fmt(fmt) "aspeed-kcs-bmc: " fmt
27 #define DEVICE_NAME "ast-kcs-bmc"
34 * LPCyE Enable LPC channel y
35 * IBFIEy Input Buffer Full IRQ Enable for LPC channel y
36 * IRQxEy Assert SerIRQ x for LPC channel y (Deprecated, use IDyIRQX, IRQXEy)
37 * IDyIRQX Use the specified 4-bit SerIRQ for LPC channel y
38 * SELyIRQX SerIRQ polarity for LPC channel y (low: 0, high: 1)
39 * IRQXEy Assert the SerIRQ specified in IDyIRQX for LPC channel y
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnuvoton,npcm845-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nuvoton,npcm845-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tomer Maimon <tmaimon77@gmail.com>
13 The Nuvoton BMC NPCM8XX Pin Controller multi-function routed through
20 const: nuvoton,npcm845-pinctrl
25 '#address-cells':
28 '#size-cells':
44 gpio-controller: true
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/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-common-npcm7xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
7 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&gic>;
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <25000000>;
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/linux/drivers/irqchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
119 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
127 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
177 maps the internal interrupts sources to PCIe interrupt.
180 will be called irq-lan966x-oic.
221 bool "J-Core integrated AIC" if COMPILE_TEST
225 Support for the J-Core integrated AIC.
236 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
239 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
244 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
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/linux/Documentation/devicetree/bindings/tpm/
H A Dtcg,tpm-tis-mmio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/tpm/tcg,tpm-tis-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MMIO-accessed Trusted Platform Module conforming to TCG TIS specification
10 - Lukas Wunner <lukas@wunner.de>
13 The Trusted Computing Group (TCG) has defined a multi-vendor standard
15 one of them being LPC (via MMIO). The standard is named:
17 …tps://trustedcomputinggroup.org/resource/pc-client-work-group-pc-client-specific-tpm-interface-spe…
22 - enum:
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/linux/arch/arm/include/asm/
H A Dassembler.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2000 Russell King
10 * Do not include any C declarations in this file - it is included by
21 #include <asm/opcodes-virt.h>
22 #include <asm/asm-offsets.h>
26 #include <asm/uaccess-asm.h>
77 * set to write-allocate (this would need further testing on XScale when WA
95 * Enable and disable interrupts
128 stmdb sp!, {r0-r3, ip, lr}
132 ldmia sp!, {r0-r3, ip, lr}
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/linux/arch/powerpc/boot/dts/
H A Dmpc5121.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2008 Freescale Semiconductor Inc.
8 #include <dt-bindings/clock/mpc512x-clock.h>
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&ipic>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <0x20>; /* 32 bytes */
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