Lines Matching +full:lpc +full:- +full:interrupts

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nuvoton,npcm845-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Tomer Maimon <tmaimon77@gmail.com>
13   The Nuvoton BMC NPCM8XX Pin Controller multi-function routed through
20     const: nuvoton,npcm845-pinctrl
25   '#address-cells':
28   '#size-cells':
44       gpio-controller: true
46       '#gpio-cells':
52       interrupts:
55       gpio-ranges:
59       - gpio-controller
60       - '#gpio-cells'
61       - reg
62       - interrupts
63       - gpio-ranges
65   '-mux$':
66     $ref: pinmux-node.yaml#
83                   r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1,
106                 pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
125     $ref: pincfg-node.yaml#
133           pattern: '^GPIO([0-9]|[0-9][0-9]|1[0-9][0-9]|2[0-4][0-9]|25[0-6])'
135       bias-disable: true
137       bias-pull-up: true
139       bias-pull-down: true
141       input-enable: true
143       output-low: true
145       output-high: true
147       drive-push-pull: true
149       drive-open-drain: true
151       input-debounce:
158       slew-rate:
164       drive-strength:
170   - $ref: pinctrl.yaml#
173   - compatible
174   - ranges
175   - '#address-cells'
176   - '#size-cells'
177   - nuvoton,sysgcr
182   - |
183     #include <dt-bindings/interrupt-controller/arm-gic.h>
184     #include <dt-bindings/gpio/gpio.h>
187       #address-cells = <2>;
188       #size-cells = <2>;
191         compatible = "nuvoton,npcm845-pinctrl";
193         #address-cells = <1>;
194         #size-cells = <1>;
198           gpio-controller;
199           #gpio-cells = <2>;
201           interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
202           gpio-ranges = <&pinctrl 0 0 32>;
205         fanin0_pin: fanin0-mux {
210         pin34_slew: pin34-slew {
212           bias-disable;