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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
H A Dmt8183.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8183-larb-port.h>
13 #include <dt-bindings/power/mt8183-power.h>
14 #include <dt-bindings/reset/mt8183-resets.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/thermal/thermal.h>
[all …]
/linux/Documentation/devicetree/bindings/iommu/
H A Dqcom,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies legacy IOMMU implementations
10 - Konrad Dybcio <konradybcio@kernel.org>
13 Qualcomm "B" family devices which are not compatible with arm-smmu have
14 a similar looking IOMMU, but without access to the global register space
16 to non-secure vs secure interrupt line.
21 - items:
[all …]
H A Dqcom,apq8064-iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/iommu/qcom,apq8064-iommu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm APQ8064 IOMMU
11 - David Heidelberg <david@ixit.cz>
14 The MSM IOMMU is an implementation compatible with the ARM VMSA short
16 outside of the CPU, each connected to the IOMMU through a port called micro-TLB.
20 const: qcom,apq8064-iommu
24 - description: interface clock for register accesses
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H A Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
[all …]
H A Dsamsung,sysmmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iommu/samsung,sysmmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
10 - Marek Szyprowski <m.szyprowski@samsung.com>
14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
15 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
17 System MMU is an IOMMU and supports identical translation table format to
20 another capabilities like L2 TLB or block-fetch buffers to minimize translation
[all …]
H A Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
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H A Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek IOMMU Architecture Implementation
10 - Yong Wu <yong.wu@mediatek.com>
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
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/linux/Documentation/devicetree/bindings/media/
H A Dsamsung,s5p-mfc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,s5p-mfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Szyprowski <m.szyprowski@samsung.com>
11 - Aakarsh Jain <aakarsh.jain@samsung.com>
20 - enum:
21 - samsung,exynos5433-mfc # Exynos5433
22 - samsung,mfc-v5 # Exynos4
23 - samsung,mfc-v6 # Exynos5
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H A Dmediatek,mt8195-jpegdec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
17 const: mediatek,mt8195-jpgdec
19 power-domains:
25 Points to the respective IOMMU block with master port as argument, see
26 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
29 "#address-cells":
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H A Dmediatek,mt8195-jpegenc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
17 const: mediatek,mt8195-jpgenc
19 power-domains:
25 Points to the respective IOMMU block with master port as argument, see
26 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
29 "#address-cells":
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include <dt-bindings/clock/exynos5250.h>
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
46 #address-cells = <1>;
47 #size-cells = <0>;
49 cpu-map {
62 compatible = "arm,cortex-a15";
65 clock-names = "cpu";
66 operating-points-v2 = <&cpu0_opp_table>;
[all …]
H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
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/linux/arch/arm/boot/dts/mediatek/
H A Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Dt600x-die0.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 nco: clock-controller@28e03c000 {
11 compatible = "apple,t6000-nco", "apple,nco";
14 #clock-cells = <1>;
17 aic: interrupt-controller@28e100000 {
18 compatible = "apple,t6000-aic", "apple,aic2";
19 #interrupt-cells = <4>;
20 interrupt-controller;
23 reg-names = "core", "event";
24 power-domains = <&ps_aic>;
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 #address-cells = <1>;
14 #size-cells = <1>;
18 frame-number = <1>;
30 #mbox-cells = <1>;
32 clock-names = "apb_pclk";
35 smmu_gpu: iommu@2b400000 {
[all …]
H A Dmorello-sdp.dts1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
6 /dts-v1/;
11 compatible = "arm,morello-sdp", "arm,morello";
18 stdout-path = "serial0:115200n8";
21 dpu_aclk: clock-350000000 {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <350000000>;
26 clock-output-names = "aclk";
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra264.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 #include <dt-bindings/clock/nvidia,tegra264.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/nvidia,tegra264.h>
7 #include <dt-bindings/reset/nvidia,tegra264.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14 numa-node-id = <0>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8976.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/power/qcom-rpmpd.h>
18 interrupt-parent = <&intc>;
[all …]
/linux/Documentation/devicetree/bindings/gpu/
H A Dnvidia,gk20a.txt4 - compatible: "nvidia,<gpu>"
6 - nvidia,gk20a
7 - nvidia,gm20b
8 - nvidia,gp10b
9 - nvidia,gv11b
10 - reg: Physical base address and length of the controller's registers.
12 - first entry for bar0
13 - second entry for bar1
14 - interrupts: Must contain an entry for each entry in interrupt-names.
15 See ../interrupt-controller/interrupts.txt for details.
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77995.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a77995-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
[all …]
H A Dr8a77951.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7795-sysc.h>
19 #address-cells = <2>;
20 #size-cells = <2>;
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <0>;
[all …]
H A Dr8a774e1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774e1-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
[all …]
/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-soc.dtsi1 // SPDX-License-Identifier: GPL-2.0
10 interrupt-parent = <&gic0>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 /include/ "amd-seattle-clks.dtsi"
16 gic0: interrupt-controller@e1101000 {
17 compatible = "arm,gic-400", "arm,cortex-a15-gic";
18 interrupt-controller;
19 #interrupt-cells = <3>;
20 #address-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra74x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
16 compatible = "arm,cortex-a15";
18 operating-points-v2 = <&cpu0_opp_table>;
21 clock-names = "cpu";
23 clock-latency = <300000>; /* From omap-cpufreq driver */
26 #cooling-cells = <2>; /* min followed by max */
28 vbb-supply = <&abb_mpu>;
40 compatible = "arm,cortex-a15-pmu";
41 interrupt-parent = <&wakeupgen>;
[all …]

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