| /titanic_41/usr/src/uts/common/io/nxge/ |
| H A D | nxge_intr.c | 30 * This file manages the interrupts for a hybrid I/O (hio) device.
31 * In the future, it may manage interrupts for all Neptune-based
75 nxge_intr_t *interrupts; /* The global interrupt data. */ in nxge_intr_add() local
102 interrupts = (nxge_intr_t *)&nxge->nxge_intr_type; in nxge_intr_add()
106 if ((status2 = ddi_intr_add_handler(interrupts->htable[vector], in nxge_intr_add()
115 interrupts->intr_added++; in nxge_intr_add()
118 if ((status2 = ddi_intr_enable(interrupts->htable[vector])) in nxge_intr_add()
127 interrupts->intr_enabled = B_TRUE; in nxge_intr_add()
165 nxge_intr_t *interrupts; /* The global interrupt data. */ in nxge_intr_remove() local
194 interrupts = (nxge_intr_t *)&nxge->nxge_intr_type; in nxge_intr_remove()
[all …]
|
| /titanic_41/usr/src/uts/common/io/i40e/ |
| H A D | i40e_intr.c | 22 * There are a couple different sets of interrupts that we need to worry about:
24 * - Interrupts from receive queues
25 * - Interrupts from transmit queues
26 * - 'Other Interrupts', such as the administrative queue
28 * 'Other Interrupts' are asynchronous events such as a link status change event
33 * interrupts from the 'Other Interrupts' section, we need to clear the PBA and
36 * Interrupts from the transmit and receive queues indicates that our requests
45 * All devices supported by this driver support three kinds of interrupts:
47 * o Extended Message Signaled Interrupts (MSI-X)
48 * o Message Signaled Interrupts (MSI)
[all …]
|
| /titanic_41/usr/src/man/man9f/ |
| H A D | ddi_intr_get_nintrs.9f | 8 ddi_intr_get_nintrs, ddi_intr_get_navail \- return number of interrupts
58 Pointer to number of interrupts of the given type that are supported by the
89 Pointer to number of interrupts of the given type that are currently available
96 The \fBddi_intr_get_nintrs()\fR function returns the number of interrupts of
98 return, the number of supported interrupts is returned as an integer pointed to
102 If the hardware device is not found to support any interrupts of the given
107 The \fBddi_intr_get_navail()\fR function returns the number of interrupts of a
109 successful return, the number of available interrupts is returned as an integer
114 all interrupts be allocated. The host software can then use policy-based
115 decisions to determine how many interrupts are made available to the device.
[all …]
|
| H A D | ddi_intr_alloc.9f | 8 ddi_intr_alloc, ddi_intr_free \- allocate or free interrupts for a given
77 Number of interrupts requested. The \fIcount\fR should not exceed the total
78 number of interrupts supported by the device, as returned by a call to
88 Pointer to the number of interrupts actually allocated
115 The \fBddi_intr_alloc()\fR function allocates interrupts of the interrupt type
117 If \fBddi_intr_alloc()\fR allocates any interrupts, it returns the actual
118 number of interrupts allocated in the integer pointed to by the \fIactualp\fR
123 Specific interrupts are always specified by the combination of interrupt
125 interrupt, typically as defined by the devices \fBinterrupts\fR property. For
126 PCI fixed interrupts, \fIinum\fR refers to the interrupt number. The \fIinum\fR
[all …]
|
| H A D | ddi_intr_set_nreq.9f | 8 ddi_intr_set_nreq \- set the number of interrupts requested for a device driver
40 Number of interrupts requested.
46 The \fBddi_intr_set_nreq()\fR function changes the number of interrupts
58 interrupts supported by the device hardware, as reported by a call to the
60 notifying it in cases when it must release any previously allocated interrupts,
61 or when it is allowed to allocate more interrupts as a result of its new
66 already consuming interrupts, and if it has a registered callback handler that
142 that are using MSI-X interrupts (interrupt type \fBDDI_INTR_TYPE_MSIX\fR).
143 Attempts to use this function for any other type of interrupts fails with
147 The total number of interrupts requested by the driver is initially defined by
|
| H A D | ddi_cb_register.9f | 159 For interrupt resource management, the driver has more available interrupts.
170 For interrupt resource management, the driver has fewer available interrupts.
171 The driver must release any previously allocated interrupts in excess of what
185 represents how many interrupts have been added or removed from the total number
195 interrupts that are available to it, but it is required to manage its
196 allocations so that it never uses more interrupts than are currently available.
324 /* Get number of supported interrupts */
397 /* Disable and free interrupts */
471 /* Update actual count of available interrupts */
482 /* Update actual count of available interrupts */
[all …]
|
| H A D | ddi_intr_enable.9f | 10 interrupts
74 Number of interrupts
107 Number of interrupts
117 The \fBddi_intr_block_enable()\fR function enables a range of interrupts given
128 \fBddi_intr_block_enable()\fR function is useful for enabling MSI interrupts
148 The \fBddi_intr_block_disable()\fR function disables a range of interrupts
159 \fBddi_intr_block_disable()\fR function is useful for disabling MSI interrupts
167 the \fBddi_intr_block_enable()\fR function was used to enable the interrupts.
240 If a device driver that uses \fBMSI\fR and \fBMSI-X\fR interrupts resets the
|
| H A D | ddi_intr_get_hilevel_pri.9f | 35 High-level interrupts must be handled without using system services that
36 manipulate thread or process states, because such interrupts are not blocked by
53 devices always generate low level interrupts. On some machines, however,
54 interrupts are high-level above the scheduler level and on other machines they
55 are not. Devices such as those those using SBus interrupts or VME bus level 6
56 or 7 interrupts must use the \fBddi_intr_get_hilevel_pri()\fR function to test
|
| H A D | ddi_intr_hilevel.9f | 52 High level interrupts must be handled without using system services that
53 manipulate thread or process states, because these interrupts are not blocked
70 support will always generate low level interrupts, however some devices, for
71 example those using SBus or VME bus level 6 or 7 interrupts must use this test
72 because on some machines those interrupts are high level (above the scheduler
|
| H A D | ddi_intr_dup_handler.9f | 9 interrupts
57 The \fBddi_intr_dup_handler()\fR function is a feature for MSI-X interrupts
63 For example, if 2 MSI-X interrupts were allocated to a driver and 32 interrupts
64 were supported on the device, the driver could alias the 2 interrupts it
129 not to support MSI-X interrupts.
175 /* Get the count of how many MSI-X interrupts we dup */
|
| /titanic_41/usr/src/uts/sun4v/sys/ |
| H A D | machintreg.h | 45 * MAXVINTRS is the number of interrupts we require to be allocated
46 * in the system intr_vec_table in addition to the hardware interrupts.
47 * These interrupts will be used by the sun4v cnex driver for its Logical
48 * Domain Channels. Each LDC requires a pair of interrupts, (RX/TX),
49 * and the total number of interrupts required will depend on the
61 * each LDC requires a pair of interrupts we need to add the
62 * capacity for ~4096 interrupts to the system interrupt table.
64 * We start allocating the LDC interrupts at MINVINTR_COOKIE.
|
| /titanic_41/usr/src/uts/common/io/scsi/adapters/smrt/ |
| H A D | smrt_interrupts.c | 54 * 6.XX firmware versions, MSI-X interrupts do not appear in smrt_try_msix()
61 dev_err(smrt->smrt_dip, CE_NOTE, "!trying MSI-X interrupts " in smrt_try_msix()
125 dev_err(dip, CE_WARN, "could not count %s interrupts", in smrt_interrupts_alloc()
130 dev_err(dip, CE_WARN, "no %s interrupts supported", in smrt_interrupts_alloc()
137 "interrupts", smrt_interrupt_type_name(type)); in smrt_interrupts_alloc()
141 dev_err(dip, CE_WARN, "no %s interrupts available", in smrt_interrupts_alloc()
180 dev_err(dip, CE_WARN, "could not get support interrupts"); in smrt_interrupts_setup()
212 * interrupts. Note that the use of fixed interrupts has been in smrt_interrupts_setup()
214 * result in interrupts stopping completely at random times. in smrt_interrupts_setup()
224 * We were unable to allocate any interrupts. in smrt_interrupts_setup()
[all …]
|
| /titanic_41/usr/src/uts/i86pc/os/ |
| H A D | intr.c | 30 * interrupts.
41 * With the switch to the 8259A, level mode interrupts became possible. For a
42 * long time on i86pc the 8259A was the only way to handle interrupts and it
67 * interrupts, the lapic provides a way for generating inter-processor
68 * interrupts (IPI) which are the basis for CPU cross calls and CPU pokes.
122 * Generally most interrupts fire below LOCK_LEVEL.
136 * interrupts. In the apix driver each local apic has its own independent set
137 * of interrupts, whereas the pcplusmp driver only has a single global set of
138 * interrupts. This is why pcplusmp only supports a finite number of interrupts
141 * change the number of interrupts available, just the number of processors
[all …]
|
| /titanic_41/usr/src/uts/sun4/os/ |
| H A D | intr.c | 84 * gatekeeper preventing soft interrupts from being queued. In this capacity,
86 * it can end up set while iv_pending is reset, preventing soft interrupts from
121 * Register these software interrupts for ddi timer. in intr_init()
122 * Software interrupts up to the level 10 are supported. in intr_init()
141 * of soft interrupts. Soft interrupts can't be dispatched until after in intr_init()
170 * Trigger software interrupts dedicated to ddi timer.
384 /* Clear pending interrupts at this level if the list is empty */ in intr_dequeue_req()
406 * Take the specified CPU out of participation in interrupts.
428 * Allow the specified CPU to participate in interrupts.
430 * because of bound threads, in order to resume processing interrupts.
[all …]
|
| /titanic_41/usr/src/uts/common/io/ |
| H A D | i8042.c | 43 * Unfortunately, soft interrupts are implemented poorly. Each additional
82 * 0x02: 0 = Disable aux port interrupts. (1=Enable aux port interrupts)
83 * 0x01: 0 = Disable main port interrupts. (1=Enable main port interrupts)
111 * regardless of the number of interrupts in the prom node.
112 * This is important, as registering for all interrupts on
114 * of spurious interrupts (for Tadpole, the first 2 interrupts
250 * be set to force the nexus to use interrupts.
431 * If any children still have regs mapped or interrupts in i8042_cleanup()
470 /* Stop the controller from generating interrupts */ in i8042_cleanup()
476 * Remove the interrupts in the reverse order in in i8042_cleanup()
[all …]
|
| /titanic_41/usr/src/uts/i86pc/ml/ |
| H A D | amd64.il | 69 / enable interrupts
76 / disable interrupts
83 / disable interrupts and return value describing if interrupts were enabled
164 * This function should be called with interrupts already disabled
166 * Note that "sti" will only enable interrupts at the end of the
|
| H A D | ia32.il | 56 / enable interrupts
63 / disable interrupts
70 / disable interrupts and return value describing if interrupts were enabled
160 * This function should be called with interrupts already disabled
162 * Note that "sti" will only enable interrupts at the end of the
|
| /titanic_41/usr/src/cmd/mdb/i86pc/modules/uppc/ |
| H A D | uppc.c | 89 * By default, on all x86 systems ::interrupts from uppc gets in uppc_interrupt_dump()
90 * loaded first. For APIC systems the ::interrupts from either in uppc_interrupt_dump()
102 return (mdb_call_dcmd("apix`interrupts", in uppc_interrupt_dump()
106 return (mdb_call_dcmd("pcplusmp`interrupts", in uppc_interrupt_dump()
162 { "interrupts", "?[-di]", "print interrupts", uppc_interrupt_dump,
164 { "softint", "?[-d]", "print soft interrupts", soft_interrupt_dump,
|
| /titanic_41/usr/src/uts/common/xen/public/hvm/ |
| H A D | params.h | 70 * interrupts that have been missed due to preemption. Deliver missed
71 * interrupts when the vcpu is rescheduled and advance the vcpu's virtual
74 * As above, missed interrupts are delivered, but guest time always tracks
77 * No missed interrupts are held pending. Instead, to ensure ticks are
82 * Missed interrupts are collapsed together and delivered as one 'late tick'.
106 /* Boolean: Enable aligning all periodic vpts to reduce interrupts */
|
| /titanic_41/usr/src/uts/common/os/ |
| H A D | cpu_intr.c | 47 * in I/O interrupts.
57 * Return the next on-line CPU handling interrupts.
77 * cpu_intr_count - count how many CPUs are handling I/O interrupts.
96 * Enable I/O interrupts on this CPU, if they are disabled.
109 * cpu_intr_disable - redirect I/O interrupts targetted at this CPU.
112 * interrupts, because it's stupid to take the last CPU out
|
| /titanic_41/usr/src/cmd/intrd/ |
| H A D | intrd.pl | 143 # with multiple MSI interrupts.
175 # processor is "on-line". If not, it isn't accepting interrupts
267 # All MSI interrupts of a device instance share a single MSI address.
270 # interrupts for MSI devices must be moved to the same CPU at the same
273 # Since all interrupts will be on the same CPU on these platforms, all
274 # interrupts can be consolidated into one ivec entry. For such devices,
320 # in that all CPUs and interrupts cover a similar span of time.
341 # {"avgintrnsec"} avg number of nsec spent in interrupts, per cpu
462 " interrupts")) {
635 # reconfiguration of the interrupts
[all …]
|
| /titanic_41/usr/src/uts/sun4u/io/ |
| H A D | panther_asm.s | 144 ! since we disable interrupts, we don't need to do kpreempt_disable()
147 wrpr %g0, %g1, %pstate ! disable interrupts
216 ! since we disable interrupts, we don't need to do kpreempt_disable()
219 wrpr %g0, %g1, %pstate ! disable interrupts
273 ! since we disable interrupts, we don't need to do kpreempt_disable()
276 wrpr %g0, %g1, %pstate ! disable interrupts
341 ! since we disable interrupts, we don't need to do kpreempt_disable()
344 wrpr %g0, %g1, %pstate ! disable interrupts
399 ! since we disable interrupts, we don't need to do kpreempt_disable()
402 wrpr %g0, %g1, %pstate ! disable interrupts
[all …]
|
| /titanic_41/usr/src/uts/common/io/chxge/com/ |
| H A D | mv88x201x.c | 77 /* Enable PHY LASI interrupts. */ in mv88x201x_interrupt_enable()
80 /* Enable Marvell interrupts through Elmer0. */ in mv88x201x_interrupt_enable()
93 /* Disable PHY LASI interrupts. */ in mv88x201x_interrupt_disable()
96 /* Disable Marvell interrupts through Elmer0. */ in mv88x201x_interrupt_disable()
126 /* Clear PHY LASI interrupts. */ in mv88x201x_interrupt_clear()
135 /* Clear Marvell interrupts through Elmer0. */ in mv88x201x_interrupt_clear()
146 /* Clear interrupts */ in mv88x201x_interrupt_handler()
149 /* We have only enabled link change interrupts and so in mv88x201x_interrupt_handler()
|
| /titanic_41/usr/src/uts/sun4/sys/ |
| H A D | ivintr.h | 43 * interrupts.
45 * NOTE: Need two single target software interrupts per cpu for cyclics.
74 * dynamically using kmem cache method. For the hardware interrupts, one per
75 * vector with unique pil basis, i.e, interrupts sharing the same ino and the
78 * Used by Hardware and Single target Software interrupts.
98 * Used by Multi target Software interrupts.
|
| /titanic_41/usr/src/man/man4/ |
| H A D | sbus.4 | 63 \fB\fBinterrupts\fR\fR
102 Only devices that generate interrupts need to provide \fBinterrupts\fR
141 We want to add an \fBinterrupts\fR property while we are developing the
142 firmware and driver so that we can start to experiment with interrupts. The
143 device can generate interrupts at \fBSBus\fR level 3. Additionally, we want to
|