| /illumos-gate/usr/src/uts/sun4u/opl/io/pcicmu/ |
| H A D | pcmu_intr.c | 64 * pcmu_unclaimed_intr_max within the time limit, then all interrupts
112 * There is a count of unclaimed interrupts kept on a per-ino basis. If at
118 * interrupts on that ino. The state machine will only be idled again if a
176 pcmu_ib_ino_info_t *ino_p; /* pulse interrupts have no ino */ in pcmu_add_intr()
334 * interrupts are torn down by their respective block destroy routines:
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| /illumos-gate/usr/src/uts/sun4u/sys/ |
| H A D | sysiosbus.h | 84 /* Interrupts */
200 * interrupts. There is an algorithm to calculate their bit shift.
374 int par_nintr; /* number of interrupts */
375 struct sysiointrspec *par_intr; /* array of possible interrupts */
397 /* Used for legacy interrupts */
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| /illumos-gate/usr/src/uts/i86pc/io/ |
| H A D | mp_platform_misc.c | 152 * for those interrupts (like MSI/X) that don't have a physical IRQ.
355 * Both add and delspl are complicated by the fact that different interrupts
358 * 1a. with interrupts at different IPLs
359 * 1b. with interrupts at same IPL
528 * If there are more interrupts at a higher IPL, we don't need in apic_delspl_common()
666 * If there are still active interrupts, we are done. in apic_delspl_common()
1201 /* setup I/O APIC entry for non-MSI/X interrupts */ in apic_setup_irq_table()
1232 * dip may be NULL for interrupts not associated with a device driver, in apic_bind_intr()
1233 * such as the ACPI SCI or HPET interrupts. In that case just use the in apic_bind_intr()
1351 * Mark vector as being in the process of being deleted. Interrupts
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| /illumos-gate/usr/src/uts/common/io/cxgbe/firmware/ |
| H A D | t6fw_cfg.txt | 269 # Interrupts, and two extra interrupts per function for Firmware Events (or a
270 # Forwarded Interrupt Queue) and General Interrupts per function.
273 # # Forwarded Interrupts
274 # NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and
275 # # General Interrupts
278 # their interrupts forwarded to another set of Forwarded Interrupt Queues.
599 # Ingress Queues/w Free Lists and Interrupts: 526
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| H A D | t4fw_cfg.txt | 217 # Interrupts, and two extra interrupts per function for Firmware Events (or a
218 # Forwarded Interrupt Queue) and General Interrupts per function.
221 # # Forwarded Interrupts
222 # NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and
223 # # General Interrupts
226 # their interrupts forwarded to another set of Forwarded Interrupt Queues.
558 # Ingress Queues/w Free Lists and Interrupts: 526
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| H A D | t5fw_cfg.txt | 252 # Interrupts, and two extra interrupts per function for Firmware Events (or a
253 # Forwarded Interrupt Queue) and General Interrupts per function.
256 # # Forwarded Interrupts
257 # NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and
258 # # General Interrupts
261 # their interrupts forwarded to another set of Forwarded Interrupt Queues.
609 # Ingress Queues/w Free Lists and Interrupts: 526
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| /illumos-gate/usr/src/uts/sun4u/io/px/ |
| H A D | px_asm_4u.S | 45 ! Interrupts will be disabled for the duration of the read, to prevent
55 rdpr %pstate, %o4 ! Disable interrupts if not already
94 tst %g2 ! No need to reenable interrupts
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| /illumos-gate/usr/src/uts/i86pc/os/ |
| H A D | cpr_impl.c | 131 * Set machine up to take interrupts
221 * Enable interrupts on this cpu. in i_cpr_save_context()
222 * Do not bind interrupts to this CPU's local APIC until in i_cpr_save_context()
223 * the CPU is ready to receive interrupts. in i_cpr_save_context()
242 * Disable interrupts on this CPU so that PSM knows not to bind in i_cpr_save_context()
243 * interrupts here on resume until the CPU has executed in i_cpr_save_context()
693 * Enable interrupts on boot cpu. in i_cpr_power_down()
872 * Clear the IDT as interrupts will be off and a limit of 0 will cause in init_real_mode_platter()
922 * this with interrupts disabled. in i_cpr_start_cpu()
964 (void) spl0(); /* enable interrupts */ in i_cpr_start_cpu()
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| /illumos-gate/usr/src/man/man9f/ |
| H A D | Intro.9f | 116 interrupts.
117 Most device drivers are always going to be executing low-level interrupts.
124 When executing high-level interrupts, the thread may only execute a limited
792 The same is true for other things like interrupts, event notifications,
1202 Interrupts are a central part of the role of device drivers and one of
1204 Interrupts come in different types: fixed, MSI, and MSI-X.
1207 For example, MSI and MSI-X interrupts are generally specific to PCI and
1210 needs to do is to discover what type of interrupts it supports with
1213 MSI-X, then MSI, and finally fixed interrupts, and try to allocate
1214 interrupts.
[all …]
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| /illumos-gate/usr/src/uts/intel/io/pci-ide/ |
| H A D | pci-ide.c | 409 * nodes with the appropriate "reg", "assigned-addresses" and "interrupts"
417 * interrupts=0
431 * interrupts=0
444 * interrupts=14
449 * interrupts=15
504 /* interrupts property is required */ in pciide_initchild()
511 * this needs to be changed, do it via the interrupts in pciide_initchild()
515 "interrupts", -1); in pciide_initchild()
517 /* setup compatibility mode interrupts */ in pciide_initchild()
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| /illumos-gate/usr/src/uts/sun4v/vm/ |
| H A D | mach_sfmmu_asm.S | 198 * From resume we call sfmmu_setctx_sec with interrupts disabled.
199 * But we can also get called from C with interrupts enabled. So,
203 /* If interrupts are not disabled, then disable them */
207 wrpr %g1, PSTATE_IE, %pstate /* disable interrupts */
219 wrpr %g0, %g1, %pstate /* enable interrupts */
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| /illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/ |
| H A D | ecore_int_api.h | 108 * @brief This function creates an update command for interrupts that is
138 /* Both segments (interrupts & acks) are written to same place address; in ecore_sb_ack()
205 * @brief ecore_int_igu_enable_int - enable device interrupts
216 * @brief ecore_int_igu_disable_int - disable device interrupts
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| /illumos-gate/usr/src/man/man8/ |
| H A D | psrset.8 | 204 Disables interrupts for all processors within the specified processor set. See
207 If some processors in the set cannot have their interrupts disabled, the other
208 processors still have their interrupts disabled, and the command reports an
246 Enable interrupts for all processors within the specified processor set. See
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| H A D | psradm.8 | 41 disable interrupts for an \fBoff-line\fR processor. Thus, the actual effect of
81 interrupts.
328 system that can service interrupts needed by the system.
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| /illumos-gate/usr/src/uts/i86pc/sys/ |
| H A D | apic_common.h | 89 /* vector at which error interrupts come in */
94 /* vector at which performance counter overflow interrupts come in */
98 /* vector at which CMCI interrupts come in */
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| /illumos-gate/usr/src/uts/sun4/io/px/ |
| H A D | px_var.h | 95 devino_t *px_inos; /* inos from "interrupts" prop */
96 int px_inos_len; /* "interrupts" length */
138 /* px_pm_flags definitions used with interrupts and FMA code */
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| /illumos-gate/usr/src/man/man2/ |
| H A D | p_online.2 | 53 it is not interruptible by attached I/O devices. Typically, interrupts, when
57 one processor must always be available to service system clock interrupts.
127 interruptible processor in the system, or it handles interrupts that cannot be
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| /illumos-gate/usr/src/uts/common/os/ |
| H A D | cpu_event.c | 195 * The target CPU disables interrupts before clearing corresponding bit and
664 * interrupts enabled or disabled, so we need to make sure interrupts in cpu_idle_enter()
694 * cpu_idle_enter runs with interrupts in cpu_idle_enter()
696 * also be called with interrupts disabled. in cpu_idle_enter()
698 * enable the interrupts, if they can also in cpu_idle_enter()
768 * handler. When called from interrupt handler, interrupts will be in cpu_idle_exit()
769 * disabled. When called from idle thread, interrupts may be disabled in cpu_idle_exit()
773 /* Called from interrupt, interrupts are already disabled. */ in cpu_idle_exit()
1153 * Now target CPU is spinning in a pause loop with interrupts disabled. in cpu_idle_intercept_cpu()
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| /illumos-gate/usr/src/uts/intel/io/vmm/io/ |
| H A D | vatpic.c | 180 * further interrupts at that level and enables interrupts from all in vatpic_get_highest_irrpin()
182 * bearing on the levels that can generate interrupts. in vatpic_get_highest_irrpin()
230 /* No eligible interrupts on slave chip */ in vatpic_notify_intr()
243 * PIC interrupts are routed to both the Local APIC in vatpic_notify_intr()
253 * virtual wire which delivers interrupts from the PIC in vatpic_notify_intr()
258 * 3. Virtual Wire Mode via I/O APIC: PIC interrupts are in vatpic_notify_intr()
269 /* No eligible interrupts on master chip */ in vatpic_notify_intr()
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| /illumos-gate/usr/src/uts/i86xpv/io/psm/ |
| H A D | mp_platform_xpv.c | 136 * for those interrupts (like MSI/X) that don't have a physical IRQ.
307 * Both add and delspl are complicated by the fact that different interrupts
310 * 1a. with interrupts at different IPLs
311 * 1b. with interrupts at same IPL
480 * If there are more interrupts at a higher IPL, we don't need in apic_delspl_common()
618 * If there are still active interrupts, we are done. in apic_delspl_common()
1151 /* setup I/O APIC entry for non-MSI/X interrupts */ in apic_setup_irq_table()
1294 * Mark vector as being in the process of being deleted. Interrupts
1297 * addspl and delspl with interrupts disabled. Because an interrupt
1400 * Must be called with interrupts disabled and apic_ioapic_lock held
[all …]
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| /illumos-gate/usr/src/uts/i86pc/io/pcplusmp/ |
| H A D | apic_timer.c | 331 * interrupts should be generated. There is no need to support the periodic
345 * This function will enable timer interrupts.
358 * This function will disable timer interrupts.
381 * Should be called with interrupts disabled. in apic_timer_stop_count()
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| /illumos-gate/usr/src/uts/common/sys/ |
| H A D | ddi_intr.h | 136 * *nintrsp*, the number of interrupts the device supports for the
145 * *navailp*, the number of interrupts currently available for the
237 * Return DDI_FAILURE if the device has no interrupts.
311 * Like ddi_add_intr, only for system interrupts that you can trigger
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| /illumos-gate/usr/src/uts/sun4/io/ |
| H A D | ivintr.c | 74 * used for hardware and software interrupts. in init_ivintr()
109 * and single or multi target software interrupts either from the reserved
141 "target software interrupts, %d", MAX_RSVD_IVX); in iv_alloc()
147 * interrupts. Create a kmem cache for the interrupt allocation, in iv_alloc()
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| /illumos-gate/usr/src/uts/common/io/fibre-channel/fca/oce/ |
| H A D | oce_intr.c | 35 * top level function to setup interrupts
229 * function to enable interrupts
268 * function to disable interrupts
288 "Failed to disable interrupts 0x%x", ret); in oce_di()
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| /illumos-gate/usr/src/uts/common/io/rge/ |
| H A D | rge_main.c | 737 * Start chip processing, including enabling interrupts in rge_start()
1295 * Register FIXED or MSI interrupts.
1308 /* Get number of interrupts */ in rge_add_intrs()
1316 /* Get number of available interrupts */ in rge_add_intrs()
1402 * Unregister FIXED or MSI interrupts
1409 /* Disable all interrupts */ in rge_rem_intrs()
1577 * we don't support high level interrupts in the driver in rge_attach()
1623 * accesses, but with interrupts and Bus Mastering off. in rge_attach()
1627 * and allow interrupts only when everything else is set up. in rge_attach()
1700 * interrupts ... in rge_attach()
[all …]
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