| /illumos-gate/usr/src/uts/common/io/nxge/ |
| H A D | nxge_intr.c | 30 * This file manages the interrupts for a hybrid I/O (hio) device.
31 * In the future, it may manage interrupts for all Neptune-based
75 nxge_intr_t *interrupts; /* The global interrupt data. */ in nxge_intr_add() local
103 interrupts = (nxge_intr_t *)&nxge->nxge_intr_type; in nxge_intr_add()
107 if ((status2 = ddi_intr_add_handler(interrupts->htable[vector], in nxge_intr_add()
116 interrupts->intr_added++; in nxge_intr_add()
119 if ((status2 = ddi_intr_enable(interrupts->htable[vector])) in nxge_intr_add()
128 interrupts->intr_enabled = B_TRUE; in nxge_intr_add()
166 nxge_intr_t *interrupts; /* The global interrupt data. */ in nxge_intr_remove() local
195 interrupts = (nxge_intr_t *)&nxge->nxge_intr_type; in nxge_intr_remove()
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| /illumos-gate/usr/src/man/man9f/ |
| H A D | ddi_intr_get_nintrs.9f | 8 ddi_intr_get_nintrs, ddi_intr_get_navail \- return number of interrupts
53 Pointer to number of interrupts of the given type that are supported by the
84 Pointer to number of interrupts of the given type that are currently available
89 The \fBddi_intr_get_nintrs()\fR function returns the number of interrupts of
91 return, the number of supported interrupts is returned as an integer pointed to
95 If the hardware device is not found to support any interrupts of the given
100 The \fBddi_intr_get_navail()\fR function returns the number of interrupts of a
102 successful return, the number of available interrupts is returned as an integer
107 all interrupts be allocated. The host software can then use policy-based
108 decisions to determine how many interrupts are made available to the device.
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| H A D | ddi_intr_alloc.9f | 8 ddi_intr_alloc, ddi_intr_free \- allocate or free interrupts for a given
72 Number of interrupts requested. The \fIcount\fR should not exceed the total
73 number of interrupts supported by the device, as returned by a call to
83 Pointer to the number of interrupts actually allocated
108 The \fBddi_intr_alloc()\fR function allocates interrupts of the interrupt type
110 If \fBddi_intr_alloc()\fR allocates any interrupts, it returns the actual
111 number of interrupts allocated in the integer pointed to by the \fIactualp\fR
116 Specific interrupts are always specified by the combination of interrupt
118 interrupt, typically as defined by the devices \fBinterrupts\fR property. For
119 PCI fixed interrupts, \fIinum\fR refers to the interrupt number. The \fIinum\fR
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| H A D | ddi_cb_register.9f | 152 For interrupt resource management, the driver has more available interrupts.
163 For interrupt resource management, the driver has fewer available interrupts.
164 The driver must release any previously allocated interrupts in excess of what
178 represents how many interrupts have been added or removed from the total number
188 interrupts that are available to it, but it is required to manage its
189 allocations so that it never uses more interrupts than are currently available.
312 /* Get number of supported interrupts */
385 /* Disable and free interrupts */
459 /* Update actual count of available interrupts */
470 /* Update actual count of available interrupts */
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| H A D | ddi_intr_set_nreq.9f | 8 ddi_intr_set_nreq \- set the number of interrupts requested for a device driver
36 Number of interrupts requested.
40 The \fBddi_intr_set_nreq()\fR function changes the number of interrupts
52 interrupts supported by the device hardware, as reported by a call to the
54 notifying it in cases when it must release any previously allocated interrupts,
55 or when it is allowed to allocate more interrupts as a result of its new
60 already consuming interrupts, and if it has a registered callback handler that
129 that are using MSI-X interrupts (interrupt type \fBDDI_INTR_TYPE_MSIX\fR).
130 Attempts to use this function for any other type of interrupts fails with
134 The total number of interrupts requested by the driver is initially defined by
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| H A D | ddi_intr_enable.9f | 10 interrupts
69 Number of interrupts
102 Number of interrupts
110 The \fBddi_intr_block_enable()\fR function enables a range of interrupts given
121 \fBddi_intr_block_enable()\fR function is useful for enabling MSI interrupts
141 The \fBddi_intr_block_disable()\fR function disables a range of interrupts
152 \fBddi_intr_block_disable()\fR function is useful for disabling MSI interrupts
160 the \fBddi_intr_block_enable()\fR function was used to enable the interrupts.
228 If a device driver that uses \fBMSI\fR and \fBMSI-X\fR interrupts resets the
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| H A D | ddi_intr_get_hilevel_pri.9f | 30 High-level interrupts must be handled without using system services that
31 manipulate thread or process states, because such interrupts are not blocked by
48 devices always generate low level interrupts. On some machines, however,
49 interrupts are high-level above the scheduler level and on other machines they
50 are not. Devices such as those those using SBus interrupts or VME bus level 6
51 or 7 interrupts must use the \fBddi_intr_get_hilevel_pri()\fR function to test
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| H A D | ddi_intr_hilevel.9f | 46 High level interrupts must be handled without using system services that
47 manipulate thread or process states, because these interrupts are not blocked
64 support will always generate low level interrupts, however some devices, for
65 example those using SBus or VME bus level 6 or 7 interrupts must use this test
66 because on some machines those interrupts are high level (above the scheduler
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| H A D | ddi_intr_dup_handler.9f | 9 interrupts
51 The \fBddi_intr_dup_handler()\fR function is a feature for MSI-X interrupts
57 For example, if 2 MSI-X interrupts were allocated to a driver and 32 interrupts
58 were supported on the device, the driver could alias the 2 interrupts it
121 not to support MSI-X interrupts.
166 /* Get the count of how many MSI-X interrupts we dup */
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| /illumos-gate/usr/src/uts/common/io/i40e/ |
| H A D | i40e_intr.c | 23 * There are a couple different sets of interrupts that we need to worry about:
25 * - Interrupts from receive queues
26 * - Interrupts from transmit queues
27 * - 'Other Interrupts', such as the administrative queue
29 * 'Other Interrupts' are asynchronous events such as a link status change event
34 * interrupts from the 'Other Interrupts' section, we need to clear the PBA and
37 * Interrupts from the transmit and receive queues indicates that our requests
46 * All devices supported by this driver support three kinds of interrupts:
48 * o Extended Message Signaled Interrupts (MSI-X)
49 * o Message Signaled Interrupts (MSI)
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| /illumos-gate/usr/src/uts/i86pc/os/ |
| H A D | intr.c | 30 * interrupts.
41 * With the switch to the 8259A, level mode interrupts became possible. For a
42 * long time on i86pc the 8259A was the only way to handle interrupts and it
67 * interrupts, the lapic provides a way for generating inter-processor
68 * interrupts (IPI) which are the basis for CPU cross calls and CPU pokes.
122 * Generally most interrupts fire below LOCK_LEVEL.
136 * interrupts. In the apix driver each local apic has its own independent set
137 * of interrupts, whereas the pcplusmp driver only has a single global set of
138 * interrupts. This is why pcplusmp only supports a finite number of interrupts
141 * change the number of interrupts available, just the number of processors
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| /illumos-gate/usr/src/uts/common/io/usb/hcd/xhci/ |
| H A D | xhci_intr.c | 21 * Interrupts in the xHCI driver are quite straightforward. We only have a
29 * One of the challenges is knowing when to claim interrupts. Generally
30 * speaking, interrupts for MSI and MSI-X are directed to a specific vector for
33 * interrupts in PCI where interrupts are shared between multiple devices.
39 * Because of this, we only check the IP bit when we're using INTx interrupts.
56 xhci_error(xhcip, "failed to block-disable interrupts: " in xhci_ddi_intr_disable()
81 xhci_error(xhcip, "failed to block-enable interrupts: " in xhci_ddi_intr_enable()
98 * Configure the device for interrupts. We need to take care of three things.
100 * then enabling interrupts themselves globally.
167 * When using shared interrupts, verify that this interrupt is for us. in xhci_intr()
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| /illumos-gate/usr/src/uts/sun4/os/ |
| H A D | intr.c | 87 * gatekeeper preventing soft interrupts from being queued. In this capacity,
89 * it can end up set while iv_pending is reset, preventing soft interrupts from
123 * Register these software interrupts for ddi timer. in intr_init()
124 * Software interrupts up to the level 10 are supported. in intr_init()
143 * of soft interrupts. Soft interrupts can't be dispatched until after in intr_init()
172 * Trigger software interrupts dedicated to ddi timer.
386 /* Clear pending interrupts at this level if the list is empty */ in intr_dequeue_req()
408 * Take the specified CPU out of participation in interrupts.
431 * Allow the specified CPU to participate in interrupts.
433 * because of bound threads, in order to resume processing interrupts.
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| /illumos-gate/usr/src/uts/sun4v/sys/ |
| H A D | machintreg.h | 45 * MAXVINTRS is the number of interrupts we require to be allocated
46 * in the system intr_vec_table in addition to the hardware interrupts.
47 * These interrupts will be used by the sun4v cnex driver for its Logical
48 * Domain Channels. Each LDC requires a pair of interrupts, (RX/TX),
49 * and the total number of interrupts required will depend on the
61 * each LDC requires a pair of interrupts we need to add the
62 * capacity for ~4096 interrupts to the system interrupt table.
64 * We start allocating the LDC interrupts at MINVINTR_COOKIE.
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| /illumos-gate/usr/src/uts/common/io/scsi/adapters/smrt/ |
| H A D | smrt_interrupts.c | 54 * 6.XX firmware versions, MSI-X interrupts do not appear in smrt_try_msix()
61 dev_err(smrt->smrt_dip, CE_NOTE, "!trying MSI-X interrupts " in smrt_try_msix()
125 dev_err(dip, CE_WARN, "could not count %s interrupts", in smrt_interrupts_alloc()
130 dev_err(dip, CE_WARN, "no %s interrupts supported", in smrt_interrupts_alloc()
137 "interrupts", smrt_interrupt_type_name(type)); in smrt_interrupts_alloc()
141 dev_err(dip, CE_WARN, "no %s interrupts available", in smrt_interrupts_alloc()
180 dev_err(dip, CE_WARN, "could not get support interrupts"); in smrt_interrupts_setup()
212 * interrupts. Note that the use of fixed interrupts has been in smrt_interrupts_setup()
214 * result in interrupts stopping completely at random times. in smrt_interrupts_setup()
224 * We were unable to allocate any interrupts. in smrt_interrupts_setup()
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| /illumos-gate/usr/src/boot/efi/include/Protocol/ |
| H A D | Cpu.h | 98 @retval EFI_SUCCESS Interrupts are enabled on the processor.
99 @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.
113 @retval EFI_SUCCESS Interrupts are disabled on the processor.
114 @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.
125 State. If interrupts are currently enabled, then TRUE is returned. If interrupts
130 interrupts are enabled and FALSE if interrupts are disabled.
173 …m InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts
174 are enabled and FALSE if interrupts are disabled.
255 /// Foundation. This includes flushing caches, enabling and disabling interrupts, hooking interrupt
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| H A D | Timer.h | 33 EFI_TIMER_ARCH_PROTOCOL driver can detect missed interrupts, then Time
66 @retval EFI_UNSUPPORTED The platform does not support timer interrupts.
82 This function adjusts the period of timer interrupts to the value specified
89 is disabled. This is not the same as disabling the CPU's interrupts.
100 timer interrupts will be disabled.
115 This function retrieves the period of timer interrupts in 100 ns units,
137 timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
147 …retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
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| /illumos-gate/usr/src/uts/common/io/ |
| H A D | i8042.c | 47 * Unfortunately, soft interrupts are implemented poorly. Each additional
86 * 0x02: 0 = Disable aux port interrupts. (1=Enable aux port interrupts)
87 * 0x01: 0 = Disable main port interrupts. (1=Enable main port interrupts)
115 * regardless of the number of interrupts in the prom node.
116 * This is important, as registering for all interrupts on
118 * of spurious interrupts (for Tadpole, the first 2 interrupts
254 * be set to force the nexus to use interrupts.
435 * If any children still have regs mapped or interrupts in i8042_cleanup()
474 /* Stop the controller from generating interrupts */ in i8042_cleanup()
480 * Remove the interrupts in the reverse order in in i8042_cleanup()
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| /illumos-gate/usr/src/uts/sun4u/io/ |
| H A D | panther_asm.S | 128 ! since we disable interrupts, we don't need to do kpreempt_disable()
131 wrpr %g0, %g1, %pstate ! disable interrupts
188 ! since we disable interrupts, we don't need to do kpreempt_disable()
191 wrpr %g0, %g1, %pstate ! disable interrupts
235 ! since we disable interrupts, we don't need to do kpreempt_disable()
238 wrpr %g0, %g1, %pstate ! disable interrupts
291 ! since we disable interrupts, we don't need to do kpreempt_disable()
294 wrpr %g0, %g1, %pstate ! disable interrupts
339 ! since we disable interrupts, we don't need to do kpreempt_disable()
342 wrpr %g0, %g1, %pstate ! disable interrupts
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| /illumos-gate/usr/src/cmd/intrd/ |
| H A D | intrd.pl | 143 # with multiple MSI interrupts.
175 # processor is "on-line". If not, it isn't accepting interrupts
267 # All MSI interrupts of a device instance share a single MSI address.
270 # interrupts for MSI devices must be moved to the same CPU at the same
273 # Since all interrupts will be on the same CPU on these platforms, all
274 # interrupts can be consolidated into one ivec entry. For such devices,
320 # in that all CPUs and interrupts cover a similar span of time.
341 # {"avgintrnsec"} avg number of nsec spent in interrupts, per cpu
462 " interrupts")) {
635 # reconfiguration of the interrupts
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| /illumos-gate/usr/src/uts/common/io/bnx/ |
| H A D | bnxint.c | 51 * Following LM routine checks for pending interrupts and in bnx_intr_priv()
137 * need to double check that interrupts are still enabled before in bnx_intr_recv()
178 * The interrupt cannot be ours. Interrupts in bnx_intr_1lvl()
221 /* Service the interrupts. */ in bnx_intr_1lvl()
229 * and reinstate the hardware's ability to assert interrupts. in bnx_intr_1lvl()
258 * Allow interrupts to touch the hardware. in bnx_intr_enable()
268 /* Allow the hardware to generate interrupts. */ in bnx_intr_enable()
275 * call to ddi_intr_disable immediately after enabling interrupts. This in bnx_intr_enable()
279 * routines that results in interrupts to no longer fire on the in bnx_intr_enable()
329 * Prevent any future interrupts to no longer touch the hardware. in bnx_intr_disable()
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| /illumos-gate/usr/src/cmd/mdb/i86pc/modules/uppc/ |
| H A D | uppc.c | 89 * By default, on all x86 systems ::interrupts from uppc gets in uppc_interrupt_dump()
90 * loaded first. For APIC systems the ::interrupts from either in uppc_interrupt_dump()
102 return (mdb_call_dcmd("apix`interrupts", in uppc_interrupt_dump()
106 return (mdb_call_dcmd("pcplusmp`interrupts", in uppc_interrupt_dump()
162 { "interrupts", "?[-di]", "print interrupts", uppc_interrupt_dump,
164 { "softint", "?[-d]", "print soft interrupts", soft_interrupt_dump,
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| /illumos-gate/usr/src/uts/common/io/sfxge/ |
| H A D | sfxge_intr.c | 120 * interrupts (the line must be shared in this case), just rearm the in sfxge_intr_line()
264 /* Enable interrupts at the bus */ in sfxge_intr_bus_enable()
351 /* Disable interrupts at the bus */ in sfxge_intr_bus_disable()
406 /* Enable interrupts at the NIC */ in sfxge_intr_nic_enable()
419 /* Test the interrupts */ in sfxge_intr_nic_enable()
437 * Check to see that all the test interrupts have been in sfxge_intr_nic_enable()
463 /* Disable interrupts at the NIC */ in sfxge_intr_nic_enable()
481 /* Disable interrupts at the NIC */ in sfxge_intr_nic_disable()
552 /* Get the number of available interrupts */ in sfxge_intr_init()
576 * Allow greater number of MSI-X interrupts than CPUs. in sfxge_intr_init()
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| /illumos-gate/usr/src/uts/common/os/ |
| H A D | cpu_intr.c | 45 * in I/O interrupts.
55 * Return the next on-line CPU handling interrupts.
75 * cpu_intr_count - count how many CPUs are handling I/O interrupts.
94 * Enable I/O interrupts on this CPU, if they are disabled.
107 * cpu_intr_disable - redirect I/O interrupts targetted at this CPU.
110 * interrupts, because it's stupid to take the last CPU out
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| /illumos-gate/usr/src/uts/common/xen/public/hvm/ |
| H A D | params.h | 70 * interrupts that have been missed due to preemption. Deliver missed
71 * interrupts when the vcpu is rescheduled and advance the vcpu's virtual
74 * As above, missed interrupts are delivered, but guest time always tracks
77 * No missed interrupts are held pending. Instead, to ensure ticks are
82 * Missed interrupts are collapsed together and delivered as one 'late tick'.
106 /* Boolean: Enable aligning all periodic vpts to reduce interrupts */
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