Lines Matching full:interrupts

23  * There are a couple different sets of interrupts that we need to worry about:
25  *   - Interrupts from receive queues
26  *   - Interrupts from transmit queues
27  *   - 'Other Interrupts', such as the administrative queue
29  * 'Other Interrupts' are asynchronous events such as a link status change event
34  * interrupts from the 'Other Interrupts' section, we need to clear the PBA and
37  * Interrupts from the transmit and receive queues indicates that our requests
46  * All devices supported by this driver support three kinds of interrupts:
48  *   o Extended Message Signaled Interrupts (MSI-X)
49  *   o Message Signaled Interrupts (MSI)
50  *   o Legacy PCI interrupts (INTx)
55  * opportunity for multiple interrupts which is what we'll focus on.
62  * interrupts is always bound to MSI-X vector zero. Next, we spread out all of
63  * the other interrupts that we have available to us over the remaining
71  * The hardware provides the means of mapping various queues to MSI-X interrupts
74  * a source of interrupts. As part of this, the hardware requires that we
100  * In this world, because the interrupts for the admin queue and traffic are
109  * the ICR0_ENA register. So instead, when enabling interrupts on the queues, we
113  * interrupts themselves are toggled (ignoring the question of interrupt
127  *   o RX interrupts
128  *   o TX interrupts
129  *   o 'Other interrupts' (link status change, admin queue, etc.)
131  * By default, we throttle 'other interrupts' the most, then TX interrupts, and
132  * then RX interrupts. The default values for these were based on trying to
134  * 'other interrupts' are not very frequent and they're not important for the
138  * On the flip side, when we're not polling, RX interrupts are very important.
140  * However, if we allow interrupts to occur too frequently, we risk a few
144  *     we can see upwards of 200k-300k interrupts per second on the system.
150  * In-between the 'other interrupts' and the TX interrupts we have the
166  *    o 20k interrupts/s for RX
167  *    o 5k interrupts/s for TX
168  *    o 2k interupts/s for 'Other Interrupts'
190 	 * No matter the interrupt mode, the ITR for other interrupts is always  in i40e_intr_set_itr()
207  * However when MSI-X interrupts are not being used, then this also enables and
208  * disables those interrupts.
234  * The next two functions enable/disable the reception of interrupts
265  * When MSI-X interrupts are being used, then we can enable the actual
266  * interrupts themselves. However, when they are not, we instead have to turn
293  * When MSI-X interrupts are being used, then we can disable the actual
294  * interrupts themselves. However, when they are not, we instead have to turn
363 	 * Take a look and verify that all other interrupts have been disabled  in i40e_intr_chip_fini()
460 	 * The 0th vector is for 'Other Interrupts' only (subject to  in i40e_intr_init_queue_msix()
523  * Enable the specified queue as a valid source of interrupts. Note, this should
544  * Disable the specified queue as a valid source of interrupts. Note, this
577 	 * Ensure that all non adminq interrupts are disabled at the chip level.  in i40e_intr_chip_init()
585 	 * Always enable all of the other-class interrupts to be on their own  in i40e_intr_chip_init()
610 	 * Set up all of the queues and map them to interrupts based on the bit  in i40e_intr_chip_init()
620 	 * Finally set all of the default ITRs for the interrupts. Note that the  in i40e_intr_chip_init()
786 	 * When using MSI-X interrupts, vector 0 is always reserved for the  in i40e_intr_msix()