| /titanic_41/usr/src/man/man9f/ |
| H A D | ddi_add_softintr.9f | 9 ddi_trigger_softintr \- software interrupt handling routines
47 interrupt interfaces referenced in \fBIntro\fR(9F). Refer to \fIWriting Device
68 The type of soft interrupt to retrieve the cookie for.
77 Pointer to a location to store the interrupt block cookie.
98 A hint value describing the type of soft interrupt to generate.
107 Pointer to a soft interrupt identifier where a returned soft interrupt
117 Optional pointer to an interrupt block cookie where a returned interrupt block
127 Optional pointer to an interrupt device cookie where a returned interrupt
137 Pointer to interrupt handler.
146 Argument for interrupt handler.
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| H A D | ddi_intr_add_softint.9f | 9 ddi_intr_get_softint_pri, ddi_intr_set_softint_pri \- software interrupt
72 Pointer to the DDI soft interrupt handle
81 Priority to associate with a soft interrupt
90 Pointer to soft interrupt handler
99 Argument for the soft interrupt handler
111 DDI soft interrupt handle
120 Additional argument for the soft interrupt handler
132 DDI soft interrupt handle
144 DDI soft interrupt handle
153 Soft interrupt priority of the handle
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| H A D | ddi_add_intr.9f | 8 ddi_add_intr, ddi_get_iblock_cookie, ddi_remove_intr \- hardware interrupt
43 interrupt interfaces referenced in \fBIntro\fR(9F). Refer to \fIWriting Device
64 Interrupt number.
73 Pointer to an interrupt block cookie.
94 Interrupt number.
103 Optional pointer to an interrupt block cookie where a returned interrupt block
113 Optional pointer to an interrupt device cookie where a returned interrupt
123 Pointer to interrupt handler.
132 Argument for interrupt handler.
153 Interrupt number.
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| H A D | ddi_intr_enable.9f | 9 ddi_intr_block_disable \- enable or disable a given interrupt or range of
53 DDI interrupt handle
65 Pointer to an array of DDI interrupt handles
86 DDI interrupt handle
98 Pointer to an array of DDI interrupt handles
113 The \fBddi_intr_enable()\fR function enables the interrupt given by the
114 interrupt handle \fIh\fR.
119 least \fB1\fR and \fIh_array\fR is pointer to a count-sized array of interrupt
126 \fBDDI_INTR_FLAG_BLOCK\fR if the device or host bridge supports the interrupt
127 block enable/disable feature for the given interrupt type. The
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| H A D | ddi_intr_dup_handler.9f | 8 ddi_intr_dup_handler \- reuse interrupt handler and arguments for MSI-X
33 Original DDI interrupt handle
42 Interrupt number to duplicate
51 Pointer to new DDI interrupt handle
58 that allows an unallocated interrupt vector of a device to use a previously
59 initialized or added primary MSI-X interrupt vector in order to share the same
60 vector address, vector data, interrupt handler, and handler arguments. This
62 Operating System to the unallocated interrupt vectors on an associated device.
69 interrupt handle has been added to the system or enabled by
71 respectively. If successful, the function returns the new interrupt handle for
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| H A D | ddi_intr_add_handler.9f | 8 ddi_intr_add_handler, ddi_intr_remove_handler \- add or remove interrupt
44 Pointer to the DDI interrupt handle
53 Pointer to interrupt handler
62 First argument for the interrupt handler
71 Second, optional, argument for the interrupt handler
83 DDI interrupt handle
89 The \fBddi_intr_add_handler()\fR function adds an interrupt handler given by
91 \fIarg1\fR and \fIarg2\fR for the previously allocated interrupt handle
93 passed as the first and second arguments, respectively, to the interrupt
95 interrupt handler.
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| H A D | ddi_cb_register.9f | 121 The device driver participates in interrupt resource management. The device
122 driver may receive additional interrupt resources from the system, but only
125 attached. Interrupt availability varies based on the overall needs of the
159 For interrupt resource management, the driver has more available interrupts.
160 The driver can allocate more interrupt vectors and then set up more interrupt
170 For interrupt resource management, the driver has fewer available interrupts.
189 If a driver participates in interrupt resource management, it must register a
192 interrupt availability has changed. The callback handler should use the
193 interrupt functions \fBddi_intr_alloc\fR(9F) and \fBddi_intr_free\fR(9F)
263 These functions can be called from kernel, non-interrupt context.
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| H A D | ddi_intr_alloc.9f | 9 interrupt type
50 Pointer to an array of DDI interrupt handles
59 Interrupt type
68 Interrupt number
109 DDI interrupt handle
115 The \fBddi_intr_alloc()\fR function allocates interrupts of the interrupt type
116 given by the \fItype\fR argument beginning at the interrupt number \fIinum\fR.
119 argument and returns the number of interrupt handles in the interrupt handle
123 Specific interrupts are always specified by the combination of interrupt
125 interrupt, typically as defined by the devices \fBinterrupts\fR property. For
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| H A D | usb_pipe_intr_xfer.9f | 8 usb_pipe_intr_xfer, usb_pipe_stop_intr_polling \- USB interrupt transfer and
40 Interrupt pipe handle on which request is made.
49 Pointer to interrupt transfer request.
72 Interrupt pipe handle on which to stop polling for data.
88 a transfer through a USB interrupt pipe. The request is passed to the host
93 There are three categories of interrupt transfers: periodic or polled
94 interrupt-IN, single-transfer interrupt-IN, and (single-transfer)
95 interrupt-OUT.
96 .SS "Periodic Interrupt-IN Transfers"
99 Periodic or polled interrupt-IN transfers execute on input requests which do
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| H A D | ddi_intr_get_cap.9f | 8 ddi_intr_get_cap, ddi_intr_set_cap \- get or set interrupt capabilities for a
9 given interrupt type
40 DDI interrupt handle
61 DDI interrupt handle
76 The \fBddi_intr_get_cap()\fR function returns the interrupt capability flags
77 for the interrupt handle \fIh\fR. Upon a successful return, the flags are
90 interrupt types. This is a read-write (RW) flag.
101 \fBDDI_INTR_TYPE_MSIX\fR interrupt types.
110 The interrupt can be masked either by the device or by the host bridge, or
120 The interrupt supports an interrupt pending bit. This is a read-only (\fBRO\fR)
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| H A D | ddi_intr_hilevel.9f | 8 ddi_intr_hilevel \- indicate interrupt handler type
24 interrupt interfaces referenced in \fBIntro\fR(9F). Refer to \fIWriting Device
42 Interrupt number.
49 interrupt is a "high level" interrupt.
57 In addition, high level interrupt handlers must take care to do a minimum of
61 A typical high level interrupt handler would put data into a circular buffer
62 and schedule a soft interrupt by calling \fBddi_trigger_softintr()\fR. The
64 initialized for the interrupt handler.
68 \fBddi_add_intr()\fR to decide which type of interrupt handler should be used.
81 indicates a high-level interrupt.
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| H A D | ddi_intr_get_hilevel_pri.9f | 9 interrupt
29 the minimum priority level for a high-level interrupt. The return priority
31 from \fBddi_intr_get_pri\fR(9F), to determine if a given interrupt priority is
32 a high-level interrupt.
40 In addition, high-level interrupt handlers must take care to do a minimum of
44 A typical high-level interrupt handler puts data into a circular buffer and
45 schedule a soft interrupt by calling \fBddi_intr_trigger_softint()\fR. The
47 for the interrupt handler.
51 \fBddi_intr_add_handler()\fR to help determine which type of interrupt handler
57 the type of interrupt handler that can be used.
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| H A D | ddi_intr_set_mask.9f | 8 ddi_intr_set_mask, ddi_intr_clr_mask \- set or clear mask for a given interrupt
36 DDI interrupt handle
42 The \fBddi_intr_set_mask()\fR function masks the given interrupt pointed to by
43 the device's interrupt handle \fIh\fR if the device or host bridge supports the
46 interrupt mask bits for the given interrupt type. In flight interrupts can
50 The \fBddi_intr_clr_mask()\fR function unmasks the given interrupt pointed by
51 the device's interrupt handle \fIh\fR if the device or host bridge supports the
56 called only if an interrupt is enabled. Otherwise the framework will return
61 temporarily masked the interrupt. A call to \fBddi_intr_clr_mask()\fR must be
63 \fBddi_intr_clr_mask()\fR when adding and enabling the interrupt.
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| /titanic_41/usr/src/uts/common/sys/ |
| H A D | ddi_intr.h | 29 * Sun DDI interrupt support definitions
43 * Interrupt related definitions.
48 * the the caller requested interrupt number to be added does not
51 #define DDI_INTR_NOTFOUND 1 /* interrupt not found error */
54 * For use by driver interrupt service routines to return to the
55 * system whether an interrupt was for the driver or not.
60 /* Hardware interrupt types */
65 /* Hardware interrupt priority must be a number within these min/max values */
73 /* Used in calls to allocate soft interrupt priority. */
77 * Interrupt flags specify certain capabilities for a given
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| H A D | ddi_intr_impl.h | 29 * Sun DDI interrupt implementation specific definitions
42 * Typedef for interrupt ops
47 DDI_INTROP_ALLOC, /* 3 allocate interrupt handle */
50 DDI_INTROP_ADDISR, /* 6 add interrupt handler */
51 DDI_INTROP_DUPVEC, /* 7 duplicate interrupt handler */
52 DDI_INTROP_ENABLE, /* 8 enable interrupt */
55 DDI_INTROP_DISABLE, /* 11 disable interrupt */
56 DDI_INTROP_REMISR, /* 12 remove interrupt handler */
57 DDI_INTROP_FREE, /* 13 free interrupt handle */
62 DDI_INTROP_GETPENDING, /* 18 get pending interrupt */
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| /titanic_41/usr/src/man/man9s/ |
| H A D | kstat_intr.9s | 8 kstat_intr \- structure for interrupt kstats
25 Interrupt statistics are kept in the \fBkstat_intr\fR structure. When
26 \fBkstat_create\fR(9F) creates an interrupt \fBkstat\fR, the \fBks_data\fR
38 An interrupt is a hard interrupt (sourced from the hardware device itself), a
39 soft interrupt (induced by the system through the use of some system interrupt
40 source), a watchdog interrupt (induced by a periodic timer call), spurious (an
41 interrupt entry point was entered but there was no interrupt to service), or
42 multiple service (an interrupt was detected and serviced just prior to
48 for auto-vectored devices in order to pinpoint any interrupt latency problems
52 Devices that have more than one interrupt of the same type should use multiple
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| /titanic_41/usr/src/uts/common/io/1394/adapters/ |
| H A D | hci1394_isr.c | 28 * Contains the core interrupt handling logic for the hci1394 driver.
29 * It also contains the routine which sets up the initial interrupt
57 * Get the iblock_cookie, make sure we are not using a high level interrupt,
58 * register our interrupt service routine.
69 /* This driver does not support running at a high level interrupt */ in hci1394_isr_init()
80 /* There should only be 1 1394 interrupt for an OpenHCI adapter */ in hci1394_isr_init()
99 * un-register our interrupt service routine.
116 * register our interrupt service routine.
125 /* Initialize interrupt handler */ in hci1394_isr_handler_init()
140 * un-register our interrupt service routine.
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| /titanic_41/usr/src/uts/common/io/i40e/ |
| H A D | i40e_intr.c | 19 * Interrupt Handling Theory
32 * interrupt. Note, we may need to do more here eventually. To re-enable the
42 * tx operations. This file is dedicated to handling and dealing with interrupt
52 * restricts us to only using a single interrupt, which isn't the interesting
57 * Interrupt Management
63 * interrupt vectors.
66 * mapped to the same interrupt. When the interrupt fires, we'll have to check
68 * interrupt is claimed.
74 * maintain a linked list of queues for each interrupt vector. While it may seem
80 * Finally, the individual interrupt vector itself has the ability to be enabled
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| /titanic_41/usr/src/uts/i86pc/os/ |
| H A D | intr.c | 28 * To understand the present state of interrupt handling on i86pc, we must
29 * first consider the history of interrupt controllers and our way of handling
32 * History of Interrupt Controllers on i86pc
37 * The first interrupt controller that attained widespread use on i86pc was
38 * the Intel 8259(A) Programmable Interrupt Controller that first saw use with
39 * the 8086. It took up to 8 interrupt sources and combined them into one
46 * Intel Advanced Programmable Interrupt Controller (APIC)
49 * microarchitecture (i686) Intel introduced a new interrupt controller.
58 * Instead of talking directly to 8259 for status, sending End Of Interrupt
64 * The number of addressable interrupt vectors was increased to 256. However
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| /titanic_41/usr/src/lib/libsqlite/test/ |
| H A D | interrupt.test | 17 # $Id: interrupt.test,v 1.4.2.1 2004/05/10 20:27:42 drh Exp $
39 # interrupt a progressively later and later points during the processing
69 do_test interrupt-1.1 {
75 interrupt_test interrupt-1.2 {DROP TABLE t1} {} 1 14
76 do_test interrupt-1.3 {
81 integrity_check interrupt-1.4
101 interrupt_test interrupt-2.2 {VACUUM} {} 100
102 do_test interrupt-2.3 {
107 do_test interrupt-2.4 {
110 integrity_check interrupt-2.5
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| /titanic_41/usr/src/uts/sun4/io/ |
| H A D | ivintr.c | 27 * Interrupt Vector Table Configuration
39 * Allocate an Interrupt Vector Table and some interrupt vector data structures
41 * interrupt vector data structure from the reserved pool, otherwise allocate it
44 static kmutex_t intr_vec_mutex; /* Protect interrupt vector table */
52 /* Reserved pool for interrupt allocation */
55 static kmutex_t intr_vec_pool_mutex; /* Protect interrupt vector pool */
57 /* Kmem cache handle for interrupt allocation */
62 * init_ivintr() - Initialize an Interrupt Vector Table.
73 * Initialize the reserved interrupt vector data structure pools in init_ivintr()
87 * fini_ivintr() - Uninitialize an Interrupt Vector Table.
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| /titanic_41/usr/src/uts/i86pc/io/apix/ |
| H A D | apix_intr.c | 74 * Insert an vector into the tail of the interrupt pending list
93 * Remove and return an vector from the head of hardware interrupt
130 * Add hardware interrupts to the interrupt pending list.
142 * The MSI interrupt not supporting per-vector masking could in apix_add_pending_hardint()
145 * Add ISR of this interrupt to the pending list for such in apix_add_pending_hardint()
146 * suspicious interrupt. in apix_add_pending_hardint()
177 * each interrupt handler as we go.
244 * Get set to run interrupt thread. in apix_do_softint_prolog()
245 * There should always be an interrupt thread since we in apix_do_softint_prolog()
264 * the interrupt thread is set to the pinned thread *before* in apix_do_softint_prolog()
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| /titanic_41/usr/src/uts/sun4u/opl/io/pcicmu/ |
| H A D | pcmu_intr.c | 29 * CMU-CH nexus interrupt handling:
30 * PCI device interrupt handler wrapper
32 * PCI device interrupt related initchild code
48 * interrupt jabber:
50 * When an interrupt line is jabbering, every time the state machine for the
56 * idled when an interrupt line is jabbering. See the comment at the
57 * beginning of pcmu_intr_wrapper() explaining how the 'interrupt jabber
63 * If the unclaimed interrupt count has reached the limit set by
65 * on this ino is blocked by not idling the interrupt state machine.
94 err_fmt_str = "!%s%d: spurious interrupt from ino 0x%x"; in pcmu_spurintr()
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| /titanic_41/usr/src/uts/sun4/os/ |
| H A D | dmv.c | 84 * modified while being used by the actual interrupt dispatch code; see
91 * dmv_add_intr is called to add a databearing mondo interrupt handler
95 * Note that if a processor receives a databearing mondo interrupt
103 * dmv_inum interrupt number for the device.
105 * routine pointer to the device's vectored interrupt
146 * 6. The handler may read the Incoming Interrupt Vector Data
147 * registers, and the Interrupt Vector Receive register, but
173 * interrupt routine in order to do further processing at normal
174 * interrupt level. It is strongly advised that drivers do
177 * soft interrupt routine. (This is analogous to the DDI
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| /titanic_41/usr/src/uts/sun4u/sys/pci/ |
| H A D | pci_ib.h | 44 * interrupt block soft state structure:
46 * Each pci node may share an interrupt block structure with its peer
47 * node or have its own private interrupt block structure.
53 pci_ign_t ib_ign; /* interrupt group # */
56 * PCI slot and onboard I/O interrupt mapping register blocks addresses:
63 * PCI slot and onboard I/O clear interrupt register block addresses:
69 * UPA expansion slot interrupt mapping register addresses:
75 * Interrupt retry register address:
80 * PCI slot and onboard I/O interrupt state diag register addresses:
100 * ih structure: one per every consumer of each ino and pil pair with interrupt
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