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/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dmpic.txt2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
14 - compatible
16 Value type: <string>
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
31 Value type: <empty>
32 Definition: Specifies that this node is an interrupt
[all …]
H A Dsrio-rmu.txt5 node is composed of three types of sub-nodes ("fsl-srio-msg-unit",
6 "fsl-srio-dbell-unit" and "fsl-srio-port-write-unit").
10 - compatible
12 Value type: <string>
13 Definition: Must include "fsl,srio-rmu-vX.Y", "fsl,srio-rmu".
18 - reg
20 Value type: <prop-encoded-array>
25 - fsl,liodn
26 Usage: optional-but-recommended (for devices with PAMU)
27 Value type: <prop-encoded-array>
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/sophgo/
H A Dsg2042-cpus.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #address-cells = <1>;
9 #size-cells = <0>;
10 timebase-frequency = <50000000>;
12 cpu-map {
260 riscv,isa-base = "rv64i";
261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
267 i-cache-block-size = <64>;
268 i-cache-size = <65536>;
269 i-cache-sets = <512>;
[all …]
H A Dsg2044-cpus.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #address-cells = <2>;
8 #size-cells = <2>;
11 #address-cells = <1>;
12 #size-cells = <0>;
13 timebase-frequency = <50000000>;
18 i-cache-block-size = <64>;
19 i-cache-size = <65536>;
20 i-cache-sets = <512>;
21 d-cache-block-size = <64>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dqcom-pm8xxx.txt1 Qualcomm PM8xxx PMIC multi-function devices
8 - compatible:
10 Value type: <string>
16 - #address-cells:
18 Value type: <u32>
21 - #size-cells:
23 Value type: <u32>
26 - interrupts:
28 Value type: <prop-encoded-array>
29 Definition: specifies the interrupt that indicates a subdevice
[all …]
H A Dstericsson,ab8500.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson Analog Baseband AB8500 and AB8505
10 - Linus Walleij <linus.walleij@linaro.org>
13 the AB8500 "Analog Baseband" is the mixed-signals integrated circuit
14 handling power management (regulators), analog-to-digital conversion
15 (ADC), battery charging, fuel gauging of the battery, battery-backed
16 RTC, PWM, USB PHY and some GPIO lines in the ST-Ericsson U8500 platforms
21 USB charging handling has changed, and it has an embedded USB-to-serial
[all …]
H A Dqcom-pm8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/qcom-pm8xxx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PM8xxx PMIC multi-function devices
10 - Satya Priya <quic_c_skakit@quicinc.com>
19 - enum:
20 - qcom,pm8058
21 - qcom,pm8821
22 - qcom,pm8901
[all …]
H A Dsprd,sc2731.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
18 - DCDCs to support CPU, memory
19 - LDOs to support both internal and external requirements
20 - Battery management system, such as charger, fuel gauge
21 - Audio codec
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-altera.txt4 - compatible:
5 - "altr,pio-1.0"
6 - reg: Physical base address and length of the controller's registers.
7 - #gpio-cells : Should be 2
8 - The first cell is the gpio offset number.
9 - The second cell is reserved and is currently unused.
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - interrupt-controller: Mark the device node as an interrupt controller
12 - #interrupt-cells : Should be 2. The interrupt type is fixed in the hardware.
13 - The first cell is the GPIO offset number within the GPIO controller.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dqcom,pdc.txt1 PDC interrupt controller
4 Power Domain Controller (PDC) that is on always-on domain. In addition to
6 interrupt controller that can be used to help detect edge low interrupts as
7 well detect interrupts when the GIC is non-operational.
9 GIC is parent interrupt controller at the highest level. Platform interrupt
12 specify PDC as their interrupt controller and request the PDC port associated
13 with the GIC interrupt. See example below.
17 - compatible:
19 Value type: <string>
20 Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc"
[all …]
H A Dmarvell,icu.txt1 Marvell ICU Interrupt Controller
2 --------------------------------
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
9 their type (NSR, SR, SEI, REI, etc).
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
22 - compatible: Should be one of:
[all …]
H A Dxlnx,intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/xlnx,intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Interrupt Controller
10 - Michal Simek <michal.simek@amd.com>
14 number of interrupts and the type of each interrupt. These details cannot
19 const: xlnx,xps-intc-1.00.a
27 power-domains:
33 "#interrupt-cells":
[all …]
H A Dopen-pic.txt4 representation of an Open PIC compliant interrupt controller. This binding is
13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
23 interrupt source. The type shall be a <u32> and the value shall be 2.
25 - #address-cells: Specifies the number of cells needed to encode an
26 address. The type shall be <u32> and the value shall be 0. As such,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dqcom,wcd9335.txt3 Qualcomm WCD9335 Codec is a standalone Hi-Fi audio codec IC, supports
5 the MSM8996, MSM8976, and MSM8956 chipsets. It has in-built
6 Soundwire controller, interrupt mux. It supports both I2S/I2C and
11 - compatible:
13 Value type: <stringlist>
21 - reg
23 Value type: <u32 u32>
26 - interrupts
28 Value type: <prop-encoded-array>
31 - interrupt-names:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dqcom,pcie.txt3 - compatible:
5 Value type: <stringlist>
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
[all …]
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Dqcom,pm8xxx-keypad.txt5 - compatible:
7 Value type: <string>
9 "qcom,pm8058-keypad"
10 "qcom,pm8921-keypad"
12 - reg:
14 Value type: <prop-encoded-array>
17 - interrupts:
19 Value type: <prop-encoded-array>
20 Definition: the first interrupt specifies the key sense interrupt
21 and the second interrupt specifies the key stuck interrupt.
[all …]
H A Dqcom,pm8xxx-pwrkey.txt5 - compatible:
7 Value type: <string>
9 "qcom,pm8058-pwrkey"
10 "qcom,pm8921-pwrkey"
12 - reg:
14 Value type: <prop-encoded-array>
17 - interrupts:
19 Value type: <prop-encoded-array>
20 Definition: the first interrupt specifies the key release interrupt
21 and the second interrupt specifies the key press interrupt.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dqcom,mdm9615-pinctrl.txt6 - compatible:
8 Value type: <string>
9 Definition: must be "qcom,mdm9615-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
23 Value type: <none>
24 Definition: identifies this node as an interrupt controller
[all …]
H A Dmediatek,mt6795-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctr
[all...]
H A Dmediatek,pinctrl-mt6795.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,pinctrl-mt6795.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Sean Wang <sean.wang@kernel.org>
18 const: mediatek,mt6795-pinctrl
20 gpio-controller: true
22 '#gpio-cells':
29 gpio-ranges:
[all …]
H A Dqcom,apq8084-pinctrl.txt6 - compatible:
8 Value type: <string>
9 Definition: must be "qcom,apq8084-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
23 Value type: <none>
24 Definition: identifies this node as an interrupt controller
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Darm,mhuv3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Cristian Marussi <cristian.marussi@arm.com>
19 Number, type and characteristics of each supported extension can be discovered
27 - Configure the MHU
28 - Send Transfers to the Receiver
29 - Optionally receive acknowledgment of a Transfer from the Receiver
32 - Configure the MHU
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dx1e80100-pmics.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/spmi/spmi.h>
12 thermal-zones {
13 pm8550-thermal {
14 polling-delay-passive = <100>;
16 thermal-sensors = <&pm8550_temp_alarm>;
22 type = "passive";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,smsm.txt9 - compatible:
11 Value type: <string>
15 - qcom,ipc-N:
17 Value type: <prop-encoded-array>
20 - phandle to a syscon node representing the apcs registers
21 - u32 representing offset to the register within the syscon
22 - u32 representing the ipc bit within the register
24 - qcom,local-host:
26 Value type: <u32>
32 - #address-cells:
[all …]
H A Dqcom,smp2p.txt4 a single 32-bit value between two processors. Each value has a single writer
9 - compatible:
11 Value type: <string>
15 - interrupts:
17 Value type: <prop-encoded-array>
18 Definition: one entry specifying the smp2p notification interrupt
20 - mboxes:
22 Value type: <prop-encoded-array>
26 - qcom,ipc:
28 Value type: <prop-encoded-array>
[all …]

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