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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Interrupt Controller
10 - Hector Martin <marcan@marcan.st>
13 The Apple Interrupt Controller is a simple interrupt controller present on
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
[all …]
H A Dapple,aic2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Interrupt Controller 2
10 - Hector Martin <marcan@marcan.st>
13 The Apple Interrupt Controller 2 is a simple interrupt controller present on
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
[all …]
H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
[all …]
H A Dbrcm,bcm6345-l1-intc.txt1 Broadcom BCM6345-style Level 1 interrupt controller
3 This block is a first level interrupt controller that is typically connected
8 - 32, 64 or 128 incoming level IRQ lines
10 - Most onchip peripherals are wired directly to an L1 input
12 - A separate instance of the register set for each CPU, allowing individual
15 - Contains one or more enable/status word pairs per CPU
17 - No atomic set/clear operations
19 - No polarity/level/edge settings
21 - No FIFO or priority encoder logic; software is expected to read all
22 2-4 status words to determine which IRQs are pending
[all …]
H A Dbrcm,bcm6345-l1-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm6345-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6345-style Level 1 interrupt controller
10 - Simon Arlott <simon@octiron.net>
13 This block is a first level interrupt controller that is typically connected
18 - 32, 64 or 128 incoming level IRQ lines
20 - Most onchip peripherals are wired directly to an L1 input
22 - A separate instance of the register set for each CPU, allowing individual
[all …]
H A Dbrcm,bcm7038-l1-intc.txt1 Broadcom BCM7038-style Level 1 interrupt controller
3 This block is a first level interrupt controller that is typically connected
4 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
9 - 64, 96, 128, or 160 incoming level IRQ lines
11 - Most onchip peripherals are wired directly to an L1 input
13 - A separate instance of the register set for each CPU, allowing individual
16 - Atomic mask/unmask operations
18 - No polarity/level/edge settings
20 - No FIFO or priority encoder logic; software is expected to read all
21 2-5 status words to determine which IRQs are pending
[all …]
H A Dbrcm,bcm7038-l1-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7038-style Level 1 interrupt controller
10 This block is a first level interrupt controller that is typically connected
11 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
16 - 64, 96, 128, or 160 incoming level IRQ lines
18 - Most onchip peripherals are wired directly to an L1 input
20 - A separate instance of the register set for each CPU, allowing individual
[all …]
/freebsd/sys/arm/arm/
H A Dpmu_fdt.c1 /*-
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
45 {"arm,armv8-pmuv3", 1},
46 {"arm,cortex-a77-pmu", 1},
47 {"arm,cortex-a76-pmu", 1},
48 {"arm,cortex-a75-pmu", 1},
49 {"arm,cortex-a73-pmu", 1},
50 {"arm,cortex-a72-pmu", 1},
51 {"arm,cortex-a65-pmu", 1},
52 {"arm,cortex-a57-pmu", 1},
[all …]
/illumos-gate/usr/src/cmd/ptools/plgrp/
H A Dplgrp.c49 #define DELIMIT_AFF '/' /* lgroup affinity from lgroups */
52 #define DELIMIT_RANGE '-' /* range of IDs (eg. lgroup) */
58 #define EXIT_NONFATAL 2 /* non-fatal errors */
63 #define HDR_PLGRP_AFF_GET " PID/LWPID HOME AFFINITY\n"
64 #define HDR_PLGRP_AFF_SET " PID/LWPID HOME AFFINITY\n"
76 #define FMT_HOME "%-6d"
78 #define FMT_THREAD "%8d/%-8d"
100 * Invalid value for lgroup affinity
102 #define LGRP_AFF_INVALID -1
109 #ifndef TEXT_DOMAIN /* should be defined by cc -D */
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos990.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
8 #include <dt-bindings/clock/samsung,exynos990.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <1>;
16 interrupt-parent = <&gic>;
29 #address-cells = <1>;
30 #size-cells = <0>;
32 cpu-map {
74 compatible = "arm,cortex-a55";
[all …]
H A Dexynos9810.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <1>;
16 interrupt-parent = <&gic>;
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu-map {
68 compatible = "arm,cortex-a55";
70 enable-method = "psci";
[all …]
H A Dexynos2200.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
8 #include <dt-bindings/clock/samsung,exynos2200-cmu.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 interrupt-parent = <&gic>;
30 xtcxo: clock-1 {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-output-names = "oscclk";
[all …]
/illumos-gate/usr/src/man/man1/
H A Dplgrp.18 plgrp \- observe and affect home lgroup and lgroup affinities of threads
12 \fBplgrp\fR [\fB-F\fR] [\fB-h\fR] \fIpid\fR |\fI core\fR [/\fIlwps\fR] ...
17 \fBplgrp\fR [\fB-F\fR] \fB-a\fR \fIlgroup_list\fR \fIpid\fR[/\fIlwps\fR] ...
22 \fBplgrp\fR [\fB-F\fR] \fB-H\fR \fIlgroup_list\fR \fIpid\fR[/\fIlwps\fR] ...
27 \fBplgrp\fR [\fB-F\fR] \fB-A\fR \fIlgroup_list\fR/\fInone\fR | \fIweak\fR |\fIstrong\fR [,...] \fIp…
37 An \fBlgroup\fR represents the set of CPU and memory-like hardware devices that
51 thread has the most affinity. Initially, the system chooses a home \fBlgroup\fR
52 for each thread, but leaves the thread's affinity for that \fBlgroup\fR set to
53 \fBnone\fR. If a thread sets a stronger affinity for an lgroup in its processor
55 thread is not bound to a CPU. The thread can be re-homed to the \fBlgroup\fR in
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt6001.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
16 #include "multi-die-cpp.h"
18 #include "t600x-common.dtsi"
21 compatible = "apple,t6001", "apple,arm-platform";
24 compatible = "simple-bus";
[all …]
/freebsd/lib/libsys/
H A Dcpuset.234 .Nd manage CPU affinity sets
57 per-thread mask to bind to a specific CPU or subset of CPUs and memory domains.
66 assignable on a per-process basis.
69 The anonymous set is a further thread-specific refinement on the assigned
83 .Bl -column CPU_LEVEL_CPUSET -offset indent
98 .Bl -column CPU_WHICH_INTRHANDLER -offset indent
105 .It Dv CPU_WHICH_INTRHANDLER Ta "id is an irq number for an interrupt handler"
112 of '-1' may be used with a
191 .Rv -std
206 .Bd -literal -offset indent
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt6779.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/clock/mt6779-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/mt6779-pinfunc.h>
15 interrupt-parent = <&sysirq>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 compatible = "arm,psci-0.2";
25 #address-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/sprd/
H A Dums9620.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
50 compatible = "arm,cortex-a55";
52 enable-method = "psci";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf500.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a5";
28 intc: interrupt-controller@40003000 {
29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>;
[all …]
/freebsd/sys/contrib/dev/acpica/common/
H A Ddmtable.c3 * Module Name: dmtable - Support for ACPI tables that contain no AML code
11 * Some or all of this work - Copyright (c) 1999 - 2025, Intel Corp.
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
108 * any of its subsidiaries will export/re-export any technical data, process,
130 * 3. Neither the names of the above-listed copyright holders nor the names
158 /* This module used for application-level code only */
191 "Vendor-defined Error Node",
225 "Fault Handling Interrupt",
[all …]
H A Ddmtbinfo3.c3 * Module Name: dmtbinfo3 - Table info for non-AML tables
11 * Some or all of this work - Copyright (c) 1999 - 2025, Intel Corp.
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
108 * any of its subsidiaries will export/re-export any technical data, process,
130 * 3. Neither the names of the above-listed copyright holders nor the names
157 /* This module used for application-level code only */
165 * - Add the C table definition to the actbl1.h or actbl2.h header.
166 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below.
[all …]
/freebsd/sys/contrib/edk2/Include/IndustryStandard/
H A DAcpi30.h4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
21 /// C-state Coordination Types
22 /// See s8.4.2.2 _CSD (C-State Dependency)
30 // See s8.4.4.5 _PSD (P-State Dependency)
374 /// Interrupt Source Override Structure
386 /// Platform Interrupt Sources Structure Definition
410 /// Non-Maskable Interrupt Source Structure
454 /// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
468 /// Platform Interrupt Sources Structure
[all …]
/illumos-gate/usr/src/boot/efi/include/IndustryStandard/
H A DAcpi30.h4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
360 /// Interrupt Source Override Structure
372 /// Platform Interrupt Sources Structure Definition
396 /// Non-Maskable Interrupt Source Structure
440 /// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
454 /// Platform Interrupt Sources Structure
469 /// Platform Interrupt Source Flags.
508 /// System Resource Affinity Table (SRAT. The rest of the table
531 /// Processor Local APIC/SAPIC Affinity Structure Definition
[all …]
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun8i-t113s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <riscv/allwinner/sunxi-d1s-t113.dtsi>
8 #include <riscv/allwinner/sunxi-d
[all...]
/illumos-gate/usr/src/uts/i86pc/sys/
H A Dmachcpuvar.h75 * A note about the hypervisor affinity bits: a one bit in the affinity mask
98 * We use %r13-r14 as scratch registers in the trampoline code,
107 * interrupt on the user page table. The CPU is going to push a bunch
112 * to the real interrupt stack once we've set %cr3).
139 uint64_t kf_unused; /* For 16-byte align */
147 * The KPTI is used to contain per-CPU data that is visible in both sets of
148 * page-tables, and hence must be page-aligned and page-sized. See
154 #define MACHCPU_PAD (MMU_PAGESIZE - MACHCPU_SIZE)
155 #define MACHCPU_PAD2 (MMU_PAGESIZE - 16 - 3 * sizeof (struct kpti_frame))
159 * x_call fields - used for interprocessor cross calls
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