xref: /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/brcm,bcm6345-l1-intc.yaml (revision ae5de77ed78ae54d86cead5604869212e8008e6b)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm6345-l1-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM6345-style Level 1 interrupt controller

maintainers:
  - Simon Arlott <simon@octiron.net>

description: >
  This block is a first level interrupt controller that is typically connected
  directly to one of the HW INT lines on each CPU.

  Key elements of the hardware design include:

    - 32, 64 or 128 incoming level IRQ lines

    - Most onchip peripherals are wired directly to an L1 input

    - A separate instance of the register set for each CPU, allowing individual
      peripheral IRQs to be routed to any CPU

    - Contains one or more enable/status word pairs per CPU

    - No atomic set/clear operations

    - No polarity/level/edge settings

    - No FIFO or priority encoder logic; software is expected to read all
      2-4 status words to determine which IRQs are pending

  If multiple reg ranges and interrupt-parent entries are present on an SMP
  system, the driver will allow IRQ SMP affinity to be set up through the
  /proc/irq/ interface.  In the simplest possible configuration, only one
  reg range and one interrupt-parent is needed.

  The driver operates in native CPU endian by default, there is no support for
  specifying an alternative endianness.

properties:
  compatible:
    const: brcm,bcm6345-l1-intc

  reg:
    description: One entry per CPU core
    minItems: 1
    maxItems: 2

  interrupt-controller: true

  "#interrupt-cells":
    const: 1

  interrupts:
    description: One entry per CPU core
    minItems: 1
    maxItems: 2

required:
  - compatible
  - reg
  - interrupt-controller
  - '#interrupt-cells'
  - interrupts

additionalProperties: false

examples:
  - |
    interrupt-controller@10000000 {
        compatible = "brcm,bcm6345-l1-intc";
        reg = <0x10000020 0x20>,
              <0x10000040 0x20>;

        interrupt-controller;
        #interrupt-cells = <1>;

        interrupts = <2>, <3>;
    };