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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-img.dtsi89 clock-indices = <IMX_LPCG_CLK_4>;
99 clock-indices = <IMX_LPCG_CLK_4>;
165 clock-indices = <IMX_LPCG_CLK_4>;
175 clock-indices = <IMX_LPCG_CLK_4>;
230 clock-indices = <IMX_LPCG_CLK_4>;
240 clock-indices = <IMX_LPCG_CLK_0>;
250 clock-indices = <IMX_LPCG_CLK_0>;
298 clock-indices = <IMX_LPCG_CLK_0>;
308 clock-indices = <IMX_LPCG_CLK_0>;
318 clock-indices = <IMX_LPCG_CLK_0>;
[all …]
H A Dimx8-ss-mipi1.dtsi33 clock-indices = <IMX_LPCG_CLK_0>;
44 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
55 clock-indices = <IMX_LPCG_CLK_0>;
65 clock-indices = <IMX_LPCG_CLK_0>;
75 clock-indices = <IMX_LPCG_CLK_0>;
85 clock-indices = <IMX_LPCG_CLK_0>;
95 clock-indices = <IMX_LPCG_CLK_0>;
105 clock-indices = <IMX_LPCG_CLK_0>;
H A Dimx8-ss-mipi0.dtsi47 clock-indices = <IMX_LPCG_CLK_0>;
57 clock-indices = <IMX_LPCG_CLK_0>;
67 clock-indices = <IMX_LPCG_CLK_0>;
77 clock-indices = <IMX_LPCG_CLK_0>;
87 clock-indices = <IMX_LPCG_CLK_0>;
97 clock-indices = <IMX_LPCG_CLK_0>;
H A Dimx8-ss-dma.dtsi211 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
223 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
235 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
247 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
259 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
271 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
283 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
295 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
307 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
488 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
[all …]
H A Dimx8qm-ss-lvds.dtsi9 clock-indices = <IMX_LPCG_CLK_4>;
15 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
21 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
58 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
H A Dimx8-ss-conn.dtsi213 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
227 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
241 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
259 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
281 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
298 clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
307 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
333 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
347 clock-indices = <IMX_LPCG_CLK_4>;
H A Dimx8-ss-lsio.dtsi237 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
257 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
277 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
297 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
317 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
337 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
357 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
377 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
H A Dimx8-ss-lvds1.dtsi33 clock-indices = <IMX_LPCG_CLK_4>;
44 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
56 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
68 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
H A Dimx8qm-ss-mipi.dtsi9 clock-indices = <IMX_LPCG_CLK_0>;
16 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
/linux/Documentation/devicetree/bindings/soc/cix/
H A Dcix,sky1-audss-cru.yaml22 clock tree. Internal AUDSS clocks are exposed via #clock-cells; indices are
25 Block-level software reset indices are exposed via #reset-cells; indices
41 Clock indices are defined in include/dt-bindings/clock/cix,sky1-audss-cru.h.
46 Reset indices are defined in include/dt-bindings/reset/cix,sky1-audss-cru.h.
/linux/lib/crypto/riscv/
H A Dsha512-riscv64-zvknhb-zvkb.S59 #define INDICES v1 macro
107 // is e8mf4. We use index-load with the i8 indices {40, 32, 8, 0},
111 vmv.v.x INDICES, t0
114 vluxei8.v FEBA, (STATEP), INDICES
115 vluxei8.v HGDC, (STATEP_C), INDICES
154 vsuxei8.v FEBA, (STATEP), INDICES
155 vsuxei8.v HGDC, (STATEP_C), INDICES
H A Dsha256-riscv64-zvknha_or_zvknhb-zvkb.S58 #define INDICES v1 macro
155 // is e8mf4. We use index-load with the i8 indices {20, 16, 4, 0},
159 vmv.v.x INDICES, t0
162 vluxei8.v FEBA, (STATEP), INDICES
163 vluxei8.v HGDC, (STATEP_C), INDICES
200 vsuxei8.v FEBA, (STATEP), INDICES
201 vsuxei8.v HGDC, (STATEP_C), INDICES
/linux/Documentation/devicetree/bindings/clock/
H A Dimx8qxp-lpcg.yaml57 clock-indices:
61 supported LPCG clock indices.
69 as the clock-indices property.
96 clock-indices = <IMX_LPCG_CLK_0>,
H A Drenesas,cpg-mstp-clocks.yaml45 clock-indices:
58 - clock-indices
73 clock-indices = <
H A Dallwinner,sun8i-h3-bus-gates-clk.yaml36 clock-indices:
49 - clock-indices
63 clock-indices = <5>, <6>, <8>,
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_vangogh.h178 uint16_t Voltage[3]; //[mV] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
179 uint16_t Current[3]; //[mA] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
180 uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
208 uint16_t Voltage[3]; //[mV] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
209 uint16_t Current[3]; //[mA] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
210 uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
H A Dsmu11_driver_if_cyan_skillfish.h59 uint32_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_GFX
60 uint32_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_GFX
61 uint32_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_GFX
H A Dsmu13_driver_if_v13_0_5.h96 uint16_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_SOC
97 uint16_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_SOC
99 uint16_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_SOC
/linux/Documentation/ABI/testing/
H A Dsysfs-driver-intel-m10-bmc-sec-update35 Description: Read only. Returns a list of indices for canceled code
43 Description: Read only. Returns a list of indices for canceled code
51 Description: Read only. Returns a list of indices for canceled code
/linux/drivers/clk/sunxi/
H A Dclk-sun8i-bus-gates.c51 number = of_property_count_u32_elems(node, "clock-indices"); in sun8i_h3_bus_gates_init()
52 of_property_read_u32_index(node, "clock-indices", number - 1, &number); in sun8i_h3_bus_gates_init()
59 of_property_for_each_u32(node, "clock-indices", index) { in sun8i_h3_bus_gates_init()
/linux/arch/x86/kernel/cpu/
H A Damd_cache_disable.c39 l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1; in amd_calc_l3_indices()
106 * cache which indices we disable therefore a simple wbinvd() in amd_l3_disable_index()
136 if (index > nb->l3_cache.indices) in amd_set_l3_disable_slot()
280 if (nb && nb->l3_cache.indices) in cache_get_priv_group()
297 if (nb && !nb->l3_cache.indices) in amd_init_l3_cache()
/linux/drivers/nvdimm/
H A Dbtt.h55 * indices (0, 2) and padding at indices (1, 3), where as the correct/updated
56 * format has log entries at indices (0, 1) and padding at indices (2, 3).
163 * @log_index: Indices of the valid log entries in a log_group
/linux/include/dt-bindings/power/
H A Draspberrypi-power.h9 /* These power domain indices are the firmware interface's indices
/linux/tools/testing/radix-tree/
H A Didr-test.c175 int indices[] = {4, 7, 9, 15, 65, 128, 1000, 99999, 0}; in idr_get_next_test() local
177 for(i = 0; indices[i]; i++) { in idr_get_next_test()
178 struct item *item = item_create(indices[i], 0); in idr_get_next_test()
179 assert(idr_alloc(&idr, item, indices[i], indices[i+1], in idr_get_next_test()
180 GFP_KERNEL) == indices[i]); in idr_get_next_test()
183 for(i = 0, nextid = 0; indices[i]; i++) { in idr_get_next_test()
185 assert(nextid == indices[i]); in idr_get_next_test()
/linux/include/uapi/rdma/
H A Drdma_user_rxe.h212 * It contains the producer and consumer indices. Is also
216 * producer and consumer indices in separate cache lines
217 * the kernel should always mask the indices to avoid accessing

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