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/linux/Documentation/devicetree/bindings/sound/
H A Dmicrochip,sama7g5-i2smcc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/microchip,sama7g5-i2smcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip I2S Multi-Channel Controller
10 - Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
13 The I2SMCC complies with the Inter-IC Sound (I2S) bus specification and
15 multi-channel audio codecs. It consists of a receiver, a transmitter and a
17 Client or Controller modes with receiver and/or transmitter active.
18 On later I2SMCC versions (starting with Microchip's SAMA7G5) I2S
[all …]
/linux/sound/soc/atmel/
H A Datmel-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Atmel I2S controller
29 * ---- I2S Controller Register map ----
40 #define ATMEL_I2SC_THR 0x0024 /* Transmitter Holding Register */
44 * ---- Control Register (Write-only) ----
47 #define ATMEL_I2SC_CR_RXDIS BIT(1) /* Receiver Disable */
50 #define ATMEL_I2SC_CR_TXEN BIT(4) /* Transmitter Enable */
51 #define ATMEL_I2SC_CR_TXDIS BIT(5) /* Transmitter Disable */
55 * ---- Mode Register (Read/Write) ----
59 #define ATMEL_I2SC_MR_MODE_MASTER (1 << 0)
[all …]
H A Dmchp-i2s-mcc.c1 // SPDX-License-Identifier: GPL-2.0
3 // Driver for Microchip I2S Multi-channel controller
29 * ---- I2S Controller Register map ----
46 #define MCHP_I2SMCC_THR 0x0034 /* Transmitter Holding Register */
51 #define MCHP_I2SMCC_RHL1R 0x0048 /* Receiver Holding Left 1 Register */
52 #define MCHP_I2SMCC_RHR1R 0x004C /* Receiver Holding Right 1 Register */
60 #define MCHP_I2SMCC_THL0R 0x0060 /* Transmitter Holding Left 0 Register */
61 #define MCHP_I2SMCC_THR0R 0x0064 /* Transmitter Holding Right 0 Register */
63 #define MCHP_I2SMCC_THL1R 0x0068 /* Transmitter Holding Left 1 Register */
64 #define MCHP_I2SMCC_THR1R 0x006C /* Transmitter Holding Right 1 Register */
[all …]
/linux/sound/soc/xilinx/
H A Dxlnx_i2s.c1 // SPDX-License-Identifier: GPL-2.0
3 // Xilinx ASoC I2S audio support
44 return -EINVAL; in xlnx_i2s_set_sclkout_div()
46 drv_data->sysclk = 0; in xlnx_i2s_set_sclkout_div()
48 writel(div, drv_data->base + I2S_I2STIM_OFFSET); in xlnx_i2s_set_sclkout_div()
58 drv_data->sysclk = freq; in xlnx_i2s_set_sysclk()
62 if (drv_data->is_32bit_lrclk) in xlnx_i2s_set_sysclk()
65 bits_per_sample = drv_data->data_width; in xlnx_i2s_set_sysclk()
67 drv_data->ratnum.num = freq / (bits_per_sample * drv_data->channels) / 2; in xlnx_i2s_set_sysclk()
68 drv_data->ratnum.den_step = 1; in xlnx_i2s_set_sysclk()
[all …]
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa300-raumfeld-connector.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
6 #include "pxa300-raumfeld-tuneable-clock.dtsi"
10 compatible = "raumfeld,raumfeld-connector-pxa303", "marvell,pxa300";
13 compatible = "simple-audio-card";
14 simple-audio-card,name = "Raumfeld Connector";
15 #address-cells = <1>;
16 #size-cells = <0>;
18 simple-audio-card,dai-link@0 {
[all …]
/linux/include/linux/mfd/
H A Dwl1273-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * include/linux/mfd/wl1273-core.h
5 * Some definitions for the wl1273 radio receiver/transmitter chip.
17 #define WL1273_FM_DRIVER_NAME "wl1273-fm"
21 #define WL1273_RSSI_LVL_GET 1
71 /* Transmitter API */
119 #define WL1273_RDS_ON 1
123 #define WL1273_AUDIO_ANALOG 1
126 #define WL1273_MODE_TX BIT(1)
131 #define WL1273_CODEC_CHILD BIT(1)
[all …]
/linux/sound/soc/fsl/
H A Dmpc5200_psc_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // Freescale MPC5200 PSC in I2S mode
21 * PSC_I2S_RATES: sample rates supported by the I2S
23 * This driver currently only supports the PSC running in I2S slave mode,
31 * PSC_I2S_FORMATS: audio formats supported by the PSC I2S mode
44 dev_dbg(psc_dma->dev, "%s(substream=%p) p_size=%i p_bytes=%i" in psc_i2s_hw_params()
64 dev_dbg(psc_dma->dev, "invalid format\n"); in psc_i2s_hw_params()
65 return -EINVAL; in psc_i2s_hw_params()
67 out_be32(&psc_dma->psc_regs->sicr, psc_dma->sicr | mode); in psc_i2s_hw_params()
90 dev_dbg(psc_dma->dev, "psc_i2s_set_sysclk(cpu_dai=%p, dir=%i)\n", in psc_i2s_set_sysclk()
[all …]
H A Dfsl_sai.c1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26 #include "imx-pcm.h"
44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
46 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
58 return !sai->synchronou in fsl_sai_dir_is_synced()
[all...]
/linux/sound/soc/tegra/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
5 tristate "SoC Audio for the Tegra System-on-Chip"
33 tristate "Tegra20 I2S interface"
37 Tegra20 I2S interface. You will also need to select the individual
55 tristate "Tegra30 I2S interface"
59 Tegra30 I2S interface. You will also need to select the individual
82 tristate "Tegra210 I2S module"
85 Config to enable the Inter-IC Sound (I2S) Controller which
86 implements full-duplex and bidirectional and single direction
87 point-to-point serial interfaces. It can interface with I2S
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dsii902x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Boris Brezillon <boris.brezillon@free-electrons.com>
12 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
16 #include <linux/i2c-mux.h>
18 #include <linux/media-bus-format.h>
31 #include <sound/hdmi-codec.h>
39 #define SII902X_TPI_AVI_PIXEL_REP_2X 1
42 #define SII902X_TPI_CLK_RATIO_1X (1 << 6)
50 #define SII902X_TPI_AVI_INPUT_RANGE_FULL (1 << 2)
54 #define SII902X_TPI_AVI_INPUT_COLORSPACE_YUV444 (1 << 0)
[all …]
H A Dite-it66121.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2018-2019, Artem Mygaiev
10 #include <linux/media-bus-format.h>
30 #include <sound/hdmi-codec.h>
81 #define IT66121_AFE_IP_ENC BIT(1)
103 #define IT66121_HDCP_EN1P1FEAT BIT(1)
110 #define IT66121_INT_STATUS1_RX_SENS_STATUS BIT(1)
128 #define IT66121_CLK_BANK_1 1
140 #define IT66121_INT_MASK1_RX_SENS BIT(1)
150 #define IT66121_INT_CLR1_RX_SENS BIT(1)
[all …]
H A Dtda998x_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <sound/hdmi-codec.h>
25 #include <media/cec-notifier.h>
27 #include <dt-bindings/display/tda998x.h>
115 # define MAIN_CNTRL0_SR (1 << 0)
116 # define MAIN_CNTRL0_DECS (1 << 1)
117 # define MAIN_CNTRL0_DEHS (1 << 2)
118 # define MAIN_CNTRL0_CECS (1 << 3)
119 # define MAIN_CNTRL0_CEHS (1 << 4)
120 # define MAIN_CNTRL0_SCALER (1 << 7)
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dite,it6505.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Allen Chen <allen.chen@ite.com.tw>
13 - $ref: /schemas/sound/dai-common.yaml#
16 The IT6505 is a high-performance DisplayPort 1.1a transmitter,
19 and ensures robust transmission of high-quality uncompressed video
23 also encodes and transmits up to 8 channels of I2S digital audio,
30 transmission of high-definition content. Users of the IT6505 need not
38 maxItems: 1
[all …]
/linux/sound/pci/ice1712/
H A Dpsc724.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
34 * VT1722 (Envy24GT) - 6 outputs, 4 inputs (only 2 used), 24-bit/96kHz
42 * AC-Link configuration ICE_EEP2_ACLINK=0x80
43 * use I2S, not AC97
45 * I2S converters feature ICE_EEP2_I2S=0x30
46 * I2S codec has no volume/mute control feature (bug!)
47 * I2S codec does not support 96KHz or 192KHz (bug!)
48 * I2S codec 24bits
51 * Enable integrated S/PDIF transmitter
[all …]
H A Dse.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Lowlevel functions for ONKYO WAVIO SE-90PCI and SE-200PCI
7 * Copyright (c) 2007 Shin-ya Okada sh_okada(at)d4.dion.ne.jp
8 * (at) -> @
29 /* ONKYO WAVIO SE-200PCI */
38 * AC-Link configuration ICE_EEP2_ACLINK=0x80
41 * I2S converters feature ICE_EEP2_I2S=0x78
42 * I2S codec has no volume/mute control feature
43 * I2S codec supports 96KHz and 192KHz
44 * I2S codec 24bits
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32mp157c-osd32mp1-red.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) Geanix ApS 2023 - All Rights Reserved
7 /dts-v1/;
11 #include "stm32mp15xx-osd32.dtsi"
12 #include "stm32mp15xxac-pinctrl.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
19 compatible = "oct,stm32mp157c-osd32-red", "oct,stm32mp15xx-osd32", "st,stm32mp157";
26 stdout-path = "serial0:115200n8";
29 led-controller-0 {
[all …]
H A Dstm32mp15xx-dhcor-avenger96.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
8 /* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */
9 #include "stm32mp15xx-dhcor-io1v8.dtsi"
22 cec_clock: clk-cec-fixed {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
29 stdout-path = "serial0:115200n8";
32 hdmi-out {
[all …]
/linux/sound/pci/ctxfi/
H A Dcthw20k1.c1 // SPDX-License-Identifier: GPL-2.0-only
76 * Fixed-point value in 8.24 format for parameter channel */
82 u16 ctl:1;
83 u16 ccr:1;
84 u16 sa:1;
85 u16 la:1;
86 u16 ca:1;
[all...]
H A Dcthw20k2.c1 // SPDX-License-Identifier: GPL-2.0-only
76 * Fixed-point value in 8.24 format for parameter channel */
82 u16 ctl:1;
83 u16 ccr:1;
84 u16 sa:1;
85 u16 la:1;
86 u16 ca:1;
87 u16 mpr:1;
88 u16 czbfs:1; /* Clear Z-Buffers */
107 u16 enb0:1;
[all …]
/linux/sound/i2c/
H A Dcs8427.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * IEC958 (S/PDIF) receiver & transmitter by Cirrus Logic
23 MODULE_DESCRIPTION("IEC958 (S/PDIF) receiver & transmitter by Cirrus Logic");
26 #define CS8427_ADDR (0x20>>1) /* fixed address */
38 unsigned char regmap[0x14]; /* map of first 1 + 13 registers */
52 buf[1] = val; in snd_cs8427_reg_write()
55 dev_err(device->bus->card->dev, in snd_cs8427_reg_write()
57 buf[0], buf[1], err); in snd_cs8427_reg_write()
58 return err < 0 ? err : -EIO; in snd_cs8427_reg_write()
70 err = snd_i2c_sendbytes(device, &reg, 1); in snd_cs8427_reg_read()
[all …]
/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-tqmls1021a-mbls1021a.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
5 * D-82229 Seefeld, Germany.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/linux-event-codes.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/leds/leds-pca9532.h>
15 #include <dt-bindings/net/ti-dp83867.h>
[all …]
/linux/sound/soc/ti/
H A Domap-mcbsp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
23 #include "omap-mcbsp-priv.h"
24 #include "omap-mcbsp.h"
25 #include "sdma-pcm.h"
40 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id); in omap_mcbsp_dump_reg()
41 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2)); in omap_mcbsp_dump_reg()
42 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1)); in omap_mcbsp_dump_reg()
43 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2)); in omap_mcbsp_dump_reg()
44 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1)); in omap_mcbsp_dump_reg()
[all …]
/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi-qp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
6 * Author: Algea Cao <algea.cao@rock-chips.com>
29 #include <sound/hdmi-codec.h>
31 #include "dw-hdmi-qp.h"
43 * slow so we pre-compute values we expect to see.
153 regmap_write(hdmi->regm, offset, val); in dw_hdmi_qp_write()
160 regmap_read(hdmi->regm, offset, &val); in dw_hdmi_qp_read()
168 regmap_update_bits(hdmi->regm, reg, mask, data); in dw_hdmi_qp_mod()
209 return -ENOENT; in dw_hdmi_qp_match_tmds_n_table()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
59 #define ATOM_DAC_B 1
63 #define ATOM_CRTC2 1
71 #define ATOM_DIGB 1
74 #define ATOM_PPLL2 1
85 #define ENCODER_REFCLK_SRC_P2PLL 1
91 #define ATOM_SCALER2 1
94 #define ATOM_SCALER_CENTER 1
99 #define ATOM_ENABLE 1
109 #define ATOM_BLANKING 1
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
58 #define ATOM_DAC_B 1
62 #define ATOM_CRTC2 1
74 #define ATOM_DIGB 1
77 #define ATOM_PPLL2 1
102 #define ENCODER_REFCLK_SRC_P2PLL 1
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
113 #define ATOM_ENABLE 1
[all …]

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