Lines Matching +full:i2s +full:- +full:transmitter +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-only
76 * Fixed-point value in 8.24 format for parameter channel */
82 u16 ctl:1;
83 u16 ccr:1;
84 u16 sa:1;
85 u16 la:1;
86 u16 ca:1;
87 u16 mpr:1;
88 u16 czbfs:1; /* Clear Z-Buffers */
107 u16 enb0:1;
108 u16 enb1:1;
109 u16 enb2:1;
110 u16 enb3:1;
111 u16 enb4:1;
112 u16 enb5:1;
113 u16 enb6:1;
114 u16 enb7:1;
115 u16 enbsa:1;
140 u16 srcimap:1;
162 return -ENOMEM;
180 set_field(&ctl->ctl, SRCCTL_STATE, state);
181 ctl->dirty.bf.ctl = 1;
189 set_field(&ctl->ctl, SRCCTL_BM, bm);
190 ctl->dirty.bf.ctl = 1;
198 set_field(&ctl->ctl, SRCCTL_RSR, rsr);
199 ctl->dirty.bf.ctl = 1;
207 set_field(&ctl->ctl, SRCCTL_SF, sf);
208 ctl->dirty.bf.ctl = 1;
216 set_field(&ctl->ctl, SRCCTL_WR, wr);
217 ctl->dirty.bf.ctl = 1;
225 set_field(&ctl->ctl, SRCCTL_PM, pm);
226 ctl->dirty.bf.ctl = 1;
234 set_field(&ctl->ctl, SRCCTL_ROM, rom);
235 ctl->dirty.bf.ctl = 1;
243 set_field(&ctl->ctl, SRCCTL_VO, vo);
244 ctl->dirty.bf.ctl = 1;
252 set_field(&ctl->ctl, SRCCTL_ST, st);
253 ctl->dirty.bf.ctl = 1;
261 set_field(&ctl->ctl, SRCCTL_IE, ie);
262 ctl->dirty.bf.ctl = 1;
270 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
271 ctl->dirty.bf.ctl = 1;
279 set_field(&ctl->ctl, SRCCTL_BP, bp);
280 ctl->dirty.bf.ctl = 1;
288 set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
289 ctl->dirty.bf.ccr = 1;
297 set_field(&ctl->ca, SRCCA_CA, ca);
298 ctl->dirty.bf.ca = 1;
306 set_field(&ctl->sa, SRCSA_SA, sa);
307 ctl->dirty.bf.sa = 1;
315 set_field(&ctl->la, SRCLA_LA, la);
316 ctl->dirty.bf.la = 1;
324 set_field(&ctl->mpr, MPRLH_PITCH, pitch);
325 ctl->dirty.bf.mpr = 1;
331 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
337 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
343 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
355 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
364 if (ctl->dirty.bf.czbfs) {
365 /* Clear Z-Buffer registers */
375 ctl->dirty.bf.czbfs = 0;
377 if (ctl->dirty.bf.mpr) {
383 hw_write_20kx(hw, PRING_LO_HI+4*pm_idx, ctl->mpr);
386 ctl->dirty.bf.mpr = 0;
388 if (ctl->dirty.bf.sa) {
389 hw_write_20kx(hw, SRCSA+idx*0x100, ctl->sa);
390 ctl->dirty.bf.sa = 0;
392 if (ctl->dirty.bf.la) {
393 hw_write_20kx(hw, SRCLA+idx*0x100, ctl->la);
394 ctl->dirty.bf.la = 0;
396 if (ctl->dirty.bf.ca) {
397 hw_write_20kx(hw, SRCCA+idx*0x100, ctl->ca);
398 ctl->dirty.bf.ca = 0;
404 if (ctl->dirty.bf.ccr) {
405 hw_write_20kx(hw, SRCCCR+idx*0x100, ctl->ccr);
406 ctl->dirty.bf.ccr = 0;
408 if (ctl->dirty.bf.ctl) {
409 hw_write_20kx(hw, SRCCTL+idx*0x100, ctl->ctl);
410 ctl->dirty.bf.ctl = 0;
420 ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100);
421 ctl->dirty.bf.ca = 0;
423 return get_field(ctl->ca, SRCCA_CA);
428 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
438 ((struct src_mgr_ctrl_blk *)blk)->enbsa = ~(0x0);
439 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
440 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
446 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
447 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
453 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
454 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
464 if (ctl->dirty.bf.enbsa) {
468 hw_write_20kx(hw, SRCENBS, ctl->enbsa);
469 ctl->dirty.bf.enbsa = 0;
472 if ((ctl->dirty.data & (0x1 << i))) {
473 hw_write_20kx(hw, SRCENB+(i*0x100), ctl->enb[i]);
474 ctl->dirty.data &= ~(0x1 << i);
488 return -ENOMEM;
509 return -ENOMEM;
527 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
528 ctl->dirty.bf.srcimap = 1;
536 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
537 ctl->dirty.bf.srcimap = 1;
545 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
546 ctl->dirty.bf.srcimap = 1;
554 ctl->srcimap.idx = addr;
555 ctl->dirty.bf.srcimap = 1;
563 if (ctl->dirty.bf.srcimap) {
564 hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100,
565 ctl->srcimap.srcaim);
566 ctl->dirty.bf.srcimap = 0;
586 u16 amoplo:1;
587 u16 amophi:1;
604 set_field(&ctl->amoplo, AMOPLO_M, mode);
605 ctl->dirty.bf.amoplo = 1;
619 set_field(&ctl->amoplo, AMOPLO_X, x);
620 ctl->dirty.bf.amoplo = 1;
628 set_field(&ctl->amoplo, AMOPLO_Y, y);
629 ctl->dirty.bf.amoplo = 1;
637 set_field(&ctl->amophi, AMOPHI_SADR, sadr);
638 ctl->dirty.bf.amophi = 1;
646 set_field(&ctl->amophi, AMOPHI_SE, se);
647 ctl->dirty.bf.amophi = 1;
653 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
659 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
667 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
668 hw_write_20kx(hw, AMOPLO+idx*8, ctl->amoplo);
669 ctl->dirty.bf.amoplo = 0;
670 hw_write_20kx(hw, AMOPHI+idx*8, ctl->amophi);
671 ctl->dirty.bf.amophi = 0;
681 return get_field(ctl->amoplo, AMOPLO_Y);
686 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
696 return -ENOMEM;
717 return -ENOMEM;
748 u16 srtctl:1;
760 /* S/PDIF Transmitter register dirty flags */
763 u16 spos:1;
769 /* S/PDIF Transmitter control block */
784 /* I2S Transmitter/Receiver Control register */
788 /* S/PDIF Transmitter Control register */
809 u32 daoimap:1;
828 set_field(&ctl->srtctl, SRTCTL_SRCR, src);
829 ctl->dirty.bf.srtctl = 1;
837 set_field(&ctl->srtctl, SRTCTL_SRCL, src);
838 ctl->dirty.bf.srtctl = 1;
846 set_field(&ctl->srtctl, SRTCTL_RSR, rsr);
847 ctl->dirty.bf.srtctl = 1;
855 set_field(&ctl->srtctl, SRTCTL_DRAT, drat);
856 ctl->dirty.bf.srtctl = 1;
864 set_field(&ctl->srtctl, SRTCTL_EC, ec ? 1 : 0);
865 ctl->dirty.bf.srtctl = 1;
873 set_field(&ctl->srtctl, SRTCTL_ET, et ? 1 : 0);
874 ctl->dirty.bf.srtctl = 1;
882 if (ctl->dirty.bf.srtctl) {
885 hw_write_20kx(hw, SRTSCTL+0x4*idx, ctl->srtctl);
887 /* I2S SRT */
888 hw_write_20kx(hw, SRTICTL, ctl->srtctl);
890 ctl->dirty.bf.srtctl = 0;
903 return -ENOMEM;
919 ((struct dao_ctrl_blk *)blk)->spos = spos;
920 ((struct dao_ctrl_blk *)blk)->dirty.bf.spos = 1;
928 if (ctl->dirty.bf.spos) {
931 hw_write_20kx(hw, SPOS+0x4*idx, ctl->spos);
933 ctl->dirty.bf.spos = 0;
941 *spos = ((struct dao_ctrl_blk *)blk)->spos;
952 return -ENOMEM;
972 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 1);
973 ctl->dirty.bf.spictl |= (0x1 << idx);
975 /* I2S input */
977 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 1);
978 ctl->dirty.bf.i2sictl |= (0x1 << idx);
989 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 0);
990 ctl->dirty.bf.spictl |= (0x1 << idx);
992 /* I2S input */
994 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 0);
995 ctl->dirty.bf.i2sictl |= (0x1 << idx);
1006 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 1);
1007 ctl->dirty.bf.spoctl |= (0x1 << idx);
1009 /* I2S output */
1011 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 1);
1012 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1023 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 0);
1024 ctl->dirty.bf.spoctl |= (0x1 << idx);
1026 /* I2S output */
1028 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 0);
1029 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1042 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 3);
1044 case 1:
1045 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 0);
1048 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 1);
1051 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 2);
1056 set_field(&ctl->spoctl, SPOCTL_LIV << (idx*8),
1057 (conf >> 4) & 0x1); /* Non-audio */
1058 set_field(&ctl->spoctl, SPOCTL_RIV << (idx*8),
1059 (conf >> 4) & 0x1); /* Non-audio */
1060 set_field(&ctl->spoctl, SPOCTL_OS << (idx*8),
1063 ctl->dirty.bf.spoctl |= (0x1 << idx);
1065 /* I2S output */
1075 set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1076 ctl->dirty.bf.daoimap = 1;
1084 set_field(&ctl->daoimap.aim, AIM_NXT, next);
1085 ctl->dirty.bf.daoimap = 1;
1093 ctl->daoimap.idx = addr;
1094 ctl->dirty.bf.daoimap = 1;
1103 if (ctl->dirty.bf.i2sictl || ctl->dirty.bf.i2soctl) {
1105 if ((ctl->dirty.bf.i2sictl & (0x1 << i)))
1106 ctl->dirty.bf.i2sictl &= ~(0x1 << i);
1108 if ((ctl->dirty.bf.i2soctl & (0x1 << i)))
1109 ctl->dirty.bf.i2soctl &= ~(0x1 << i);
1111 hw_write_20kx(hw, I2SCTL, ctl->i2sctl);
1112 mdelay(1);
1114 if (ctl->dirty.bf.spoctl) {
1116 if ((ctl->dirty.bf.spoctl & (0x1 << i)))
1117 ctl->dirty.bf.spoctl &= ~(0x1 << i);
1119 hw_write_20kx(hw, SPOCTL, ctl->spoctl);
1120 mdelay(1);
1122 if (ctl->dirty.bf.spictl) {
1124 if ((ctl->dirty.bf.spictl & (0x1 << i)))
1125 ctl->dirty.bf.spictl &= ~(0x1 << i);
1127 hw_write_20kx(hw, SPICTL, ctl->spictl);
1128 mdelay(1);
1130 if (ctl->dirty.bf.daoimap) {
1131 hw_write_20kx(hw, DAOIMAP+ctl->daoimap.idx*4,
1132 ctl->daoimap.aim);
1133 ctl->dirty.bf.daoimap = 0;
1146 return -ENOMEM;
1148 blk->i2sctl = hw_read_20kx(hw, I2SCTL);
1149 blk->spoctl = hw_read_20kx(hw, SPOCTL);
1150 blk->spictl = hw_read_20kx(hw, SPICTL);
1208 /* Read I2S CTL. Keep original value. */
1210 i2sorg = 0x94040404; /* enable all audio out and I2S-D input */
1211 /* Program I2S with proper master sample rate and enable
1212 * the correct I2S channel. */
1215 /* Enable S/PDIF-out-A in fixed 24-bit data
1221 switch (info->msr) {
1222 case 1:
1223 i2sorg |= 1;
1235 i2sorg |= 1;
1242 /* Enable S/PDIF-in-A in fixed 24-bit data format. */
1245 mdelay(1);
1248 mdelay(1);
1260 if ((~0UL) == info->vm_pgt_phys) {
1261 dev_err(hw->card->dev,
1263 return -1;
1266 trnctl = 0x13; /* 32-bit, 4k-size page */
1267 ptp_phys_low = (u32)info->vm_pgt_phys;
1268 ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1270 trnctl |= (1 << 2);
1273 trnctl |= (1<<5);
1321 dev_alert(hw->card->dev, "PLL initialization failed!!!\n");
1322 return -EBUSY;
1336 set_field(&gctl, GCTL_EAI, 1);
1345 dev_alert(hw->card->dev, "Card Auto-init failed!!!\n");
1346 return -EBUSY;
1367 return -1;
1396 return -1;
1410 mdelay(1);
1428 if (hw->model == CTSB055X) {
1445 return -1;
1452 switch (info->msr) {
1453 case 1:
1517 data = (data & (0x1 << 7)) ? 1 : 0;
1520 data = (data & (0x1 << 7)) ? 0 : 1;
1530 switch (hw->model) {
1573 return -1;
1590 return -1;
1602 i2c_data = 0x1; /* Mic-in */
1607 i2c_data = 0x2; /* Line-in */
1615 return -1;
1640 return -1;
1652 i2c_data = 0x1; /* Mic-in */
1656 i2c_data = 0x2; /* Line-in */
1660 return -1;
1681 switch (hw->model) {
1730 return -1;
1765 if (hw->model == CTSB055X)
1766 return adc_init_SB055x(hw, info->input, info->mic20db);
1768 return adc_init_SBx(hw, info->input, info->mic20db);
1776 cap.digit_io_switch = !(hw->model == CTSB073X || hw->model == CTUAA);
1799 const u32 CTL_ = CTLBITS('C', 'T', 'L', '-');
1810 return -ENOENT;
1818 is_uaa = ((data[1] == CTLZ && data[2] == CTLL
1819 && data[3] == CTLA) || (data[1] == CTLA
1822 is_uaa = (data[1] == CTLL
1825 is_uaa = (data[1] == CTLA
1849 /* Set up X-Fi core PCI configuration space. */
1850 /* Switch to X-Fi config space with BAR0 exposed. */
1852 /* Copy UAA's BAR5 into X-Fi BAR0 */
1854 /* Switch to X-Fi config space without BAR0 exposed. */
1866 /* Switch to X-Fi mode */
1886 if (hw->irq_callback)
1887 hw->irq_callback(hw->irq_callback_data, status);
1896 struct pci_dev *pci = hw->pci;
1904 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1905 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1907 if (!hw->io_base) {
1912 if (hw->model == CTUAA)
1913 hw->io_base = pci_resource_start(pci, 5);
1915 hw->io_base = pci_resource_start(pci, 0);
1919 /* Switch to X-Fi mode from UAA mode if needed */
1920 if (hw->model == CTUAA) {
1927 if (hw->irq < 0) {
1928 err = request_irq(pci->irq, ct_20k1_interrupt, IRQF_SHARED,
1931 dev_err(hw->card->dev,
1932 "XFi: Cannot get irq %d\n", pci->irq);
1935 hw->irq = pci->irq;
1936 hw->card->sync_irq = hw->irq;
1945 hw->io_base = 0;
1967 if (hw->irq >= 0)
1968 free_irq(hw->irq, hw);
1970 hw->irq = -1;
1971 iounmap(hw->mem_base);
1972 hw->mem_base = NULL;
1974 if (hw->io_base)
1975 pci_release_regions(hw->pci);
1977 hw->io_base = 0;
1979 pci_disable_device(hw->pci);
2000 err = hw_pll_init(hw, info->rsr);
2004 /* kick off auto-init */
2011 set_field(&gctl, GCTL_EAC, 1);
2012 set_field(&gctl, GCTL_DBP, 1);
2013 set_field(&gctl, GCTL_TBP, 1);
2014 set_field(&gctl, GCTL_FBP, 1);
2015 set_field(&gctl, GCTL_ET, 1);
2026 switch (hw->model) {
2041 trn_info.vm_pgt_phys = info->vm_pgt_phys;
2046 daio_info.msr = info->msr;
2051 dac_info.msr = info->msr;
2056 adc_info.msr = info->msr;
2073 struct pci_dev *pci = hw->pci;
2077 if (hw->model == CTUAA) {
2087 /* Re-initialize card hardware. */
2094 guard(spinlock_irqsave)(&container_of(hw, struct hw20k1, hw)->reg_20k1_lock);
2095 outl(reg, hw->io_base + 0x0);
2096 return inl(hw->io_base + 0x4);
2101 guard(spinlock_irqsave)(&container_of(hw, struct hw20k1, hw)->reg_20k1_lock);
2102 outl(reg, hw->io_base + 0x0);
2103 outl(data, hw->io_base + 0x4);
2108 guard(spinlock_irqsave)(&container_of(hw, struct hw20k1, hw)->reg_pci_lock);
2109 outl(reg, hw->io_base + 0x10);
2110 return inl(hw->io_base + 0x14);
2115 guard(spinlock_irqsave)(&container_of(hw, struct hw20k1, hw)->reg_pci_lock);
2116 outl(reg, hw->io_base + 0x10);
2117 outl(data, hw->io_base + 0x14);
2121 .irq = -1,
2231 return -ENOMEM;
2233 spin_lock_init(&hw20k1->reg_20k1_lock);
2234 spin_lock_init(&hw20k1->reg_pci_lock);
2236 hw20k1->hw = ct20k1_preset;
2238 *rhw = &hw20k1->hw;
2245 if (hw->io_base)