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/linux/Documentation/devicetree/bindings/memory-controllers/ti/
H A Demif.txt3 EMIF - External Memory Interface - is an SDRAM controller used in
5 DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
11 - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
14 "ti,emif-am3352"
15 "ti,emif-am4372"
16 "ti,emif-dra7xx"
17 "ti,emif-keystone"
19 - phy-type : <u32> indicating the DDR phy type. Following are the
24 - device-handle : phandle to a "lpddr2" node representing the memory part
26 - ti,hwmods : For TI hwmods processing and omap device creation
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
26 - description: external memory clock
28 clock-names:
[all …]
H A Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
23 const: nvidia,tegra30-emc
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_calib.c2 * Copyright (c) 2010-2011 Atheros Communications Inc.
17 #include "hw.h"
18 #include "hw-ops.h"
44 switch (currCal->calData->calType) { in ar9003_hw_setup_calibration()
52 currCal->calData->calCountMax); in ar9003_hw_setup_calibration()
58 /* Kick-off cal */ in ar9003_hw_setup_calibration()
77 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9003_hw_per_calibration()
78 const struct ath9k_percal_data *cur_caldata = currCal->calData; in ar9003_hw_per_calibration()
81 if (currCal->calState == CAL_RUNNING) { in ar9003_hw_per_calibration()
87 * Accumulate cal measures for active chains in ar9003_hw_per_calibration()
[all …]
H A Dar9002_calib.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
17 #include "hw.h"
18 #include "hw-ops.h"
36 switch (ah->supp_cals & cal_type) { in ar9002_hw_is_cal_supported()
57 currCal->calData->calCountMax); in ar9002_hw_setup_calibration()
59 switch (currCal->calData->calType) { in ar9002_hw_setup_calibration()
84 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9002_hw_per_calibration()
87 if (currCal->calState == CAL_RUNNING) { in ar9002_hw_per_calibration()
91 currCal->calData->calCollect(ah); in ar9002_hw_per_calibration()
92 ah->cal_samples++; in ar9002_hw_per_calibration()
[all …]
H A Dar9003_rtt.c2 * Copyright (c) 2010-2011 Atheros Communications Inc.
17 #include "hw.h"
18 #include "hw-ops.h"
31 * a specific calibration parameter as depicted below.
32 * 0~2 - DC offset DAC calibration: loop, low, high (offsetI/Q_...)
33 * 3 - Filter cal (filterfc)
34 * 4 - RX gain settings
35 * 5 - Peak detector offset calibration (agc_caldac)
109 if (!(ah->caps.rx_chainmask & (1 << chain))) in ar9003_hw_rtt_load_hist()
113 ah->caldata->rtt_table[chain][i]); in ar9003_hw_rtt_load_hist()
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H A Deeprom_9287.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
18 #include "hw.h"
25 u16 version = le16_to_cpu(ah->eeprom.map9287.baseEepHeader.version); in ath9k_hw_ar9287_get_eeprom_ver()
33 u16 version = le16_to_cpu(ah->eeprom.map9287.baseEepHeader.version); in ath9k_hw_ar9287_get_eeprom_rev()
40 struct ar9287_eeprom *eep = &ah->eeprom.map9287; in __ath9k_hw_ar9287_fill_eeprom()
56 u16 *eep_data = (u16 *)&ah->eeprom.map9287; in __ath9k_hw_usb_ar9287_fill_eeprom()
72 if (common->bus_ops->ath_bus_type == ATH_USB) in ath9k_hw_ar9287_fill_eeprom()
82 PR_EEP("Chain0 Ant. Control", le32_to_cpu(modal_hdr->antCtrlChain[0])); in ar9287_dump_modal_eeprom()
83 PR_EEP("Chain1 Ant. Control", le32_to_cpu(modal_hdr->antCtrlChain[1])); in ar9287_dump_modal_eeprom()
84 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon)); in ar9287_dump_modal_eeprom()
[all …]
/linux/drivers/net/wireless/ath/ath10k/
H A Dcore.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
18 #include <linux/nvmem-consumer.h>
30 #include "wmi-ops.h"
60 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
476 * or 2x2 160Mhz, long-guard-interval.
527 * 1x1 160Mhz, long-guard-interval.
[all …]
H A Dcore.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
23 #include "hw.h"
47 #define ATH10K_DEFAULT_NOISE_FLOOR -95
68 /* SMBIOS type structure length (excluding strings-set) */
145 return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; in ATH10K_SKB_CB()
150 BUILD_BUG_ON(sizeof(struct ath10k_skb_rxcb) > sizeof(skb->cb)); in ATH10K_SKB_RXCB()
151 return (struct ath10k_skb_rxcb *)skb->cb; in ATH10K_SKB_RXCB()
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H A Ddebug.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
21 #include "wmi-ops.h"
37 dev_info(ar->dev, "%pV", &vaf); in ath10k_info()
52 ar->hw_params.name, in ath10k_debug_print_hwfw_info()
53 ar->target_version, in ath10k_debug_print_hwfw_info()
54 ar->bus_param.chip_id, in ath10k_debug_print_hwfw_info()
55 ar->id.subsystem_vendor, ar->id.subsystem_device); in ath10k_debug_print_hwfw_info()
64 firmware = ar->normal_mode_fw.fw_file.firmware; in ath10k_debug_print_hwfw_info()
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_util.c1 // SPDX-License-Identifier: ISC
92 struct mt76x02_dev *dev = container_of(mphy->dev, struct mt76x02_dev, in mt76x02_led_set_config()
100 mt76_wr(dev, MT_LED_S0(mphy->leds.pin), val); in mt76x02_led_set_config()
101 mt76_wr(dev, MT_LED_S1(mphy->leds.pin), val); in mt76x02_led_set_config()
103 val = MT_LED_CTRL_REPLAY(mphy->leds.pin) | in mt76x02_led_set_config()
104 MT_LED_CTRL_KICK(mphy->leds.pin); in mt76x02_led_set_config()
105 if (mphy->leds.al) in mt76x02_led_set_config()
106 val |= MT_LED_CTRL_POLARITY(mphy->leds.pin); in mt76x02_led_set_config()
142 struct ieee80211_hw *hw = mt76_hw(dev); in mt76x02_init_device() local
143 struct wiphy *wiphy = hw->wiphy; in mt76x02_init_device()
[all …]
H A Dmt76x02_mac.c1 // SPDX-License-Identifier: ISC
28 memset(dev->mphy.aggr_stats, 0, sizeof(dev->mphy.aggr_stats)); in mt76x02_mac_reset_counters()
39 if (key->keylen > 32) in mt76x02_mac_get_key_info()
42 memcpy(key_data, key->key, key->keylen); in mt76x02_mac_get_key_info()
44 switch (key->cipher) { in mt76x02_mac_get_key_info()
67 return -EOPNOTSUPP; in mt76x02_mac_shared_key_setup()
103 atomic64_set(&key->tx_pn, pn); in mt76x02_mac_wcid_sync_pn()
116 return -EOPNOTSUPP; in mt76x02_mac_wcid_set_key()
124 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); in mt76x02_mac_wcid_set_key()
126 pn = atomic64_read(&key->tx_pn); in mt76x02_mac_wcid_set_key()
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
67 enable-method = "spin-table";
68 cpu-release-addr = <0 0>; /* To be filled by loader */
69 next-level-cache = <&l2_cache_0>;
70 i-cache-size = <0x20000>;
[all …]
/linux/drivers/memory/tegra/
H A Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
508 * a min/max clock rate, these rates are contained in this array.
512 /* protect shared rate-change code path */
521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
530 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
533 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
[all …]
/linux/drivers/hid/
H A Dhid-nintendo.c1 // SPDX-License-Identifier: GPL-2.0+
3 * HID driver for Nintendo Switch Joy-Cons and Pro Controllers
5 * Copyright (c) 2019-2021 Daniel J. Ogorchock <djogorchock@gmail.com>
12 * https://gitlab.com/pjranki/joycon-linux-kernel (Peter Rankin)
16 * hid-wiimote kernel hid driver
17 * hid-logitech-hidpp driver
18 * hid-sony driver
20 * This driver supports the Nintendo Switch Joy-Cons and Pro Controllers. The
31 #include "hid-ids.h"
120 (JC_CAL_USR_LEFT_DATA_END - JC_CAL_USR_LEFT_DATA_ADDR + 1)
[all …]
/linux/drivers/bluetooth/
H A Dhci_bcm4377.c1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
11 #include <linux/dma-mapping.h>
41 * These devices only support DMA transactions inside a 32bit window
195 * Control message used to create a completion ring
229 * Control ring message used to destroy a completion ring
244 * Control message used to create a transfer ring
256 * - virtual: set if there is no associated shared memory and only the
258 * - sync: only set for the SCO rings
281 * Control ring message used to destroy a transfer ring
297 * shared memory structures. A pointer to this structure is configured inside a
[all …]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2800lib.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include <linux/crc-ccitt.h>
46 * the register while taking a REGISTER_BUSY_DELAY us delay
87 mutex_lock(&rt2x00dev->csr_mutex); in rt2800_bbp_write()
104 mutex_unlock(&rt2x00dev->csr_mutex); in rt2800_bbp_write()
112 mutex_lock(&rt2x00dev->csr_mutex); in rt2800_bbp_read()
136 mutex_unlock(&rt2x00dev->csr_mutex); in rt2800_bbp_read()
146 mutex_lock(&rt2x00dev->csr_mutex); in rt2800_rfcsr_write()
152 switch (rt2x00dev->chip.rt) { in rt2800_rfcsr_write()
179 mutex_unlock(&rt2x00dev->csr_mutex); in rt2800_rfcsr_write()
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-p1801-t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
13 model = "Asus Portable AiO P1801-T";
14 compatible = "asus,p1801-t", "nvidia,tegra30";
15 chassis-type = "convertible";
[all …]
/linux/drivers/iio/accel/
H A Dmma9553.c1 // SPDX-License-Identifier: GPL-2.0-only
46 /* Pedometer status registers (R-only) */
67 #define MMA9553_STATUS_TO_BITNUM(bit) (ffs(bit) - 9)
75 * level and is updated every time a step is detected or once a second
91 /* Status register - activity field */
173 * 1. Serialize access to HW (requested by mma9551_core API).
174 * 2. Serialize sequences that power on/off the device and access HW.
193 return (val & mask) >> (ffs(mask) - 1); in mma9553_get_bits()
198 return (current_val & ~mask) | (val << (ffs(mask) - 1)); in mma9553_set_bits()
222 data->num_events = MMA9553_EVENTS_INFO_SIZE; in mma9553_init_events()
[all …]
/linux/drivers/clk/sprd/
H A Dsc9863a-clk.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
26 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,
28 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
30 static SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c,
32 static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
34 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,
36 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0,
38 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4,
[all …]
H A Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) Copyright 2002-2010, Ralink Technology, Inc.
23 if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || in mt7601u_rf_wr()
25 return -EINVAL; in mt7601u_rf_wr()
26 if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) in mt7601u_rf_wr()
29 mutex_lock(&dev->reg_atomic_mutex); in mt7601u_rf_wr()
32 ret = -ETIMEDOUT; in mt7601u_rf_wr()
44 mutex_unlock(&dev->reg_atomic_mutex); in mt7601u_rf_wr()
47 dev_err(dev->dev, "Error: RF write %02hhx:%02hhx failed:%d!!\n", in mt7601u_rf_wr()
56 int ret = -ETIMEDOUT; in mt7601u_rf_rr()
[all …]
/linux/arch/x86/kernel/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0-only
44 * 'what should we do if we get a hw irq event on an illegal vector'.
55 * irq slots per priority level, and a 'hanging, unacked' IRQ in ack_bad_irq()
56 * holds up an irq slot - in excessive cases (when multiple in ack_bad_irq()
59 * But only ack when the APIC is enabled -AK in ack_bad_irq()
74 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count); in arch_show_interrupts()
75 seq_puts(p, " Non-maskable interrupts\n"); in arch_show_interrupts()
79 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs); in arch_show_interrupts()
84 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count); in arch_show_interrupts()
88 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs); in arch_show_interrupts()
[all …]
/linux/drivers/net/hamradio/
H A Dscc.c6 * Please use z8530drv-utils-3.0 with this version.
7 * ------------------
9 * You can find a subset of the documentation in
15 * SCC.C - Linux driver for Z8530 based HDLC cards for AX.25 *
28 The code is likely to fail, and so your kernel could --- even
29 a whole network.
32 for commercial purposes, please drop me a note. I am nosy...
37 ! before you connect a radio to the SCC board and start to transmit or !
40 For non-Amateur-Radio use please note that you might need a special
50 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
[all …]
/linux/arch/parisc/kernel/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copyright (C) 1999-2000 Grant Grundler
27 #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
36 ** between ->ack() and ->end() of the interrupt to prevent
37 ** re-interruption of a processing interrupt.
43 unsigned long eirr_bit = EIEM_MASK(d->irq); in cpu_mask_irq()
58 /* This is just a simple NOP IPI. But what it does is cause in __cpu_unmask_irq()
59 * all the other CPUs to do a set_eiem(cpu_eiem) at the end in __cpu_unmask_irq()
66 __cpu_unmask_irq(d->irq); in cpu_unmask_irq()
71 unsigned long mask = EIEM_MASK(d->irq); in cpu_ack_irq()
[all …]

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