| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | aspeed-lpc.txt | 2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
7 primary use case of the Aspeed LPC controller is as a slave on the bus
8 (typically in a Baseboard Management Controller SoC), but under certain
11 The LPC controller is represented as a multi-function device to account for the
14 * An IPMI Block Transfer[2] Controller
16 * An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
18 APB-to-LPC bridging amonst other functions.
20 * An LPC Host Interface Controller: Manages functions exposed to the host such
21 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
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| H A D | aspeed-lpc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Aspeed Low Pin Count (LPC) Bus Controller
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
17 primary use case of the Aspeed LPC controller is as a slave on the bus
18 (typically in a Baseboard Management Controller SoC), but under certain
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| /freebsd/share/man/man4/ |
| H A D | ng_hci.4 | 1 .\" Copyright (c) 2001-2002 Maksim Yevmenkin <m_evmenkin@yahoo.com>
32 .Nd Netgraph node type that is also a Bluetooth Host Controller Interface
40 node type is a Netgraph node type that implements Bluetooth Host Controller
44 Bluetooth is a short-range radio link intended to replace the cable(s)
59 The Bluetooth system provides a point-to-point connection (only two
60 Bluetooth units involved), or a point-to-multipoint connection.
61 In the point-to-multipoint connection,
68 In addition, many more slaves can remain locked to the master in a so-called
79 in different piconets on a time-division multiplex basis.
81 The piconets shall not be frequency-synchronized.
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| H A D | ahc.4 | 2 .\" SPDX-License-Identifier: BSD-3-Clause
34 .Nd Adaptec VL/ISA/PCI SCSI host adapter driver
39 .Bd -ragged -offset indent
50 .Bd -literal -offset indent
59 host adapter chips.
62 fast, ultra or ultra2 synchronous transfers depending on controller type,
66 .Tn SCSI-Select
73 the host adapter's SCSI ID.
74 For systems that store non-volatile settings in a system specific manner
75 rather than a serial eeprom directly connected to the aic7xxx controller,
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| H A D | ufshci.4 | 4 .\" SPDX-License-Identifier: BSD-2-Clause
15 .Nd Universal Flash Storage Host Controller Interface driver
19 .Bd -ragged -offset indent
25 .Bd -literal -offset indent
29 Universal Flash Storage (UFS) is a low-power, high-performance storage
30 standard composed of a host controller and a single target device.
33 .Bl -bullet
35 Initialization of the host controller and the target device
43 Operation in the legacy single-doorbell queue mode
48 After initialization, the controller is registered with the
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| /freebsd/sys/contrib/edk2/Include/Protocol/ |
| H A D | Usb2HostController.h | 3 The USB Host Controller Protocol is used by code, typically USB bus drivers,
7 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
8 SPDX-License-Identifier: BSD-2-Clause-Patent
58 /// if combines these two bitmaps into a 32-bit bitmap.
88 Retrieves the Host Controller capabilities.
91 @param MaxSpeed Host controller data transfer speed.
93 @param Is64BitCapable TRUE if controller supports 64-bit memory addressing,
96 @retval EFI_SUCCESS The host controller capabilities were retrieved successfully.
117 Provides software reset for the USB host controller.
125 supported by the host controller hardware.
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | host-generic-pci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic PCI host controller
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
16 and clock management. In fact, the controller may not even require the
21 Configuration Space is assumed to be memory-mapped (as opposed to being
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| H A D | uniphier-pcie.txt | 1 Socionext UniPhier PCIe host controller bindings
3 This describes the devicetree bindings for PCIe host controller implemented
6 UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
9 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
12 - compatible: Should be "socionext,uniphier-pcie".
13 - reg: Specifies offset and length of the register set for the device.
14 According to the reg-names, appropriate register sets are required.
15 - reg-names: Must include the following entries:
16 "dbi" - controller configuration registers
17 "link" - SoC-specific glue layer registers
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| H A D | xilinx-versal-cpm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CPM Host Controller device tree for Xilinx Versal SoCs
10 - Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
18 - xlnx,versal-cpm-host-1.00
19 - xlnx,versal-cpm5-host
20 - xlnx,versal-cpm5-host1
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| H A D | xlnx,xdma-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
18 - xlnx,xdma-host-3.00
19 - xlnx,qdma-host-3.00
23 - description: configuration region and XDMA bridge register.
24 - description: QDMA bridge register.
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| H A D | plda,xpressrich3-axi-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/plda,xpressrich3-axi-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PLDA XpressRICH PCIe host common properties
10 - Daire McNamara <daire.mcnamara@microchip.com>
11 - Kevin Xie <kevin.xie@starfivetech.com>
14 Generic PLDA XpressRICH PCIe host common properties.
17 - $ref: /schemas/pci/pci-host-bridge.yaml#
24 reg-names:
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| H A D | ti,j721e-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI Host (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - const: ti,j721e-pcie-host
17 - const: ti,j784s4-pcie-host
18 - description: PCIe controller in AM64
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| H A D | amd,versal2-mdb-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/amd,versal2-mdb-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AMD Versal2 MDB(Multimedia DMA Bridge) Host Controller
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: /schemas/pci/snps,dw-pcie.yaml#
18 const: amd,versal2-mdb-host
22 - description: MDB System Level Control and Status Register (SLCR) Base
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| /freebsd/lib/libnvmf/ |
| H A D | libnvmf.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2022-2024 Chelsio Communications, Inc.
24 * Parameters shared by all queue-pairs of an association. Note that
30 bool dynamic_controller_model; /* Controller only */
31 uint16_t max_admin_qsize; /* Controller only */
32 uint32_t max_io_qsize; /* Controller only, 0 for discovery */
35 uint8_t pda; /* Tx-side PDA. */
38 uint32_t maxr2t; /* Host only */
39 uint32_t maxh2cdata; /* Controller only */
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| /freebsd/sys/contrib/dev/acpica/common/ |
| H A D | ahids.c | 3 * Module Name: ahids - Table of ACPI/PNP _HID/_CID values
11 * Some or all of this work - Copyright (c) 1999 - 2025, Intel Corp.
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
108 * any of its subsidiaries will export/re-export any technical data, process,
130 * 3. Neither the names of the above-listed copyright holders nor the names
165 {"80860F09", "Intel PWM Controller"},
166 {"80860F0A", "Intel Atom UART Controller"},
167 {"80860F0E", "Intel SPI Controller"},
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | ti,pruss-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controlle
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| H A D | ti,sci-inta.txt | 6 be coherently processed by the host(s) in the system. A maximum
11 +-----------------------------------------+
13 | +--------------+ +------------+ |
14 m ------>| | vint | bit | | 0 |.....|63| vint0 |
15 . | +--------------+ +------------+ | +------+
16 . | . . | | HOST |
17 Globalevents ------>| . . |------>| IRQ |
19 . | . . | +------+
20 n ------>| +--------------+ +------------+ |
22 | +--------------+ +------------+ |
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| /freebsd/sys/contrib/device-tree/Bindings/ata/ |
| H A D | apm-xgene.txt | 1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
4 controllers. Each SATA controller (pair of ports) have its own node.
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
11 Second memory resource shall be the host controller
13 Third memory resource shall be the host controller
15 4th memory resource shall be the host controller
17 5th optional memory resource shall be the host
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| /freebsd/usr.sbin/ctld/ |
| H A D | ctl.conf.5 | 34 .Nd CAM Target Layer / iSCSI target / NVMeoF controller daemon configuration file
47 .Bd -literal -offset indent
50 .No auth-group Ar name No {
55 .No portal-group Ar name No {
57 .\".Dl listen-iser Ar address
58 .Dl discovery-auth-group Ar name
62 .No transport-group Ar name No {
68 .Dl auth-group Ar name
69 .Dl portal-group Ar name
76 .No controller Ar name {
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | allwinner,sun8i-h3-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-h3-usb-phy
20 - allwinner,sun50i-h616-usb-phy
24 - description: PHY Control registers
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | s3c2410-usb.txt | 1 Samsung S3C2410 and compatible SoC USB controller
6 - compatible: should be "samsung,s3c2410-ohci" for USB host controller
7 - reg: address and length of the controller memory mapped region
8 - interrupts: interrupt number for the USB OHCI controller
9 - clocks: Should reference the bus and host clocks
10 - clock-names: Should contain two strings
11 "usb-bus-host" for the USB bus clock
12 "usb-host" for the USB host clock
17 compatible = "samsung,s3c2410-ohci";
21 clock-names = "usb-bus-host", "usb-host";
|
| H A D | exynos-usb.txt | 1 Samsung Exynos SoC USB controller
8 - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
9 EHCI controller in host mode.
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupts: interrupt number to the cpu.
13 - clocks: from common clock binding: handle to usb clock.
14 - clock-names: from common clock binding: Shall be "usbhost".
15 - phys: from the *Generic PHY* bindings; array specifying phy(s) used
17 - phy-names: from the *Generic PHY* bindings; array of the names for
19 "host", "hsic0", "hsic1".
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| /freebsd/share/misc/ |
| H A D | pci_vendors | 5 # Date: 2025-12-12 03:15:02
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-2500TX V3 Ethernet
33 7a00 7A1000 Chipset Hyper Transport Bridge Controller
34 7a02 2K1000 / 7A1000 Chipset Advanced Peripheral Bus Controller
35 7a03 2K1000/2000 / 7A1000 Chipset Gigabit Ethernet Controller
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| /freebsd/sys/contrib/device-tree/Bindings/ufs/ |
| H A D | ufs-mediatek.txt | 1 * Mediatek Universal Flash Storage (UFS) Host Controller
3 UFS nodes are defined to describe on-chip UFS hardware macro.
4 Each UFS Host Controller should have its own node.
6 To bind UFS PHY with UFS host controller, the controller node should
7 contain a phandle reference to UFS M-PHY node.
10 - compatible : Compatible list, contains the following controller:
11 "mediatek,mt8183-ufshci" for MediaTek UFS host controller
13 "mediatek,mt8192-ufshci" for MediaTek UFS host controller
15 - reg : Address and length of the UFS register set.
16 - phys : phandle to m-phy.
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| /freebsd/sys/dev/ufshci/ |
| H A D | ufshci_reg.h | 1 /*-
5 * SPDX-License-Identifier: BSD-2-Clause
15 /* Host Capabilities (00h) */
16 uint32_t cap; /* Host Controller Capabiities */
17 uint32_t mcqcap; /* Multi-Circular Queue Capability Register */
19 uint32_t ext_cap; /* Extended Controller Capabilities */
22 uint32_t ahit; /* Auto-Hibernate Idle Timer */
28 uint32_t hcsext; /* Host Controller Status Extended */
29 uint32_t hcs; /* Host Controller Status */
30 uint32_t hce; /* Host Controller Enable */
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