Searched +full:hi3559av100 +full:- +full:clock (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/hisilicon,hi3559av100-clock.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Hisilicon SOC Clock for HI3559AV10010 - Dongjiu Geng <gengdongjiu@huawei.com>13 Hisilicon SOC clock control module which supports the clocks, resets and14 power domains on HI3559AV100.17 dt-bindings/clock/hi3559av100-clock.h22 - hisilicon,hi3559av100-clock[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Hisilicon Hi3559A clock driver5 * Copyright (c) 2019-2020, Huawei Tech. Co., Ltd.10 #include <linux/clk-provider.h>16 #include <dt-bindings/clock/hi3559av100-clock.h>385 val = readl_relaxed(clk->ctrl_reg1); in clk_pll_set_rate()386 val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift); in clk_pll_set_rate()387 val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift); in clk_pll_set_rate()388 val &= ~(((1 << clk->postdiv2_width) - 1) << clk->postdiv2_shift); in clk_pll_set_rate()390 val |= frac_val << clk->frac_shift; in clk_pll_set_rate()[all …]