1 // SPDX-License-Identifier: GPL-2.0-only
3  * Hisilicon Hi3559A clock driver
5  * Copyright (c) 2019-2020, Huawei Tech. Co., Ltd.
10 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/hi3559av100-clock.h>
385 	val = readl_relaxed(clk->ctrl_reg1);  in clk_pll_set_rate()
386 	val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift);  in clk_pll_set_rate()
387 	val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift);  in clk_pll_set_rate()
388 	val &= ~(((1 << clk->postdiv2_width) - 1) << clk->postdiv2_shift);  in clk_pll_set_rate()
390 	val |= frac_val << clk->frac_shift;  in clk_pll_set_rate()
391 	val |= postdiv1_val << clk->postdiv1_shift;  in clk_pll_set_rate()
392 	val |= postdiv2_val << clk->postdiv2_shift;  in clk_pll_set_rate()
393 	writel_relaxed(val, clk->ctrl_reg1);  in clk_pll_set_rate()
395 	val = readl_relaxed(clk->ctrl_reg2);  in clk_pll_set_rate()
396 	val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift);  in clk_pll_set_rate()
397 	val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift);  in clk_pll_set_rate()
399 	val |= fbdiv_val << clk->fbdiv_shift;  in clk_pll_set_rate()
400 	val |= refdiv_val << clk->refdiv_shift;  in clk_pll_set_rate()
401 	writel_relaxed(val, clk->ctrl_reg2);  in clk_pll_set_rate()
415 	val = readl_relaxed(clk->ctrl_reg1);  in clk_pll_recalc_rate()
416 	val = val >> clk->frac_shift;  in clk_pll_recalc_rate()
417 	val &= ((1 << clk->frac_width) - 1);  in clk_pll_recalc_rate()
420 	val = readl_relaxed(clk->ctrl_reg1);  in clk_pll_recalc_rate()
421 	val = val >> clk->postdiv1_shift;  in clk_pll_recalc_rate()
422 	val &= ((1 << clk->postdiv1_width) - 1);  in clk_pll_recalc_rate()
425 	val = readl_relaxed(clk->ctrl_reg1);  in clk_pll_recalc_rate()
426 	val = val >> clk->postdiv2_shift;  in clk_pll_recalc_rate()
427 	val &= ((1 << clk->postdiv2_width) - 1);  in clk_pll_recalc_rate()
430 	val = readl_relaxed(clk->ctrl_reg2);  in clk_pll_recalc_rate()
431 	val = val >> clk->fbdiv_shift;  in clk_pll_recalc_rate()
432 	val &= ((1 << clk->fbdiv_width) - 1);  in clk_pll_recalc_rate()
435 	val = readl_relaxed(clk->ctrl_reg2);  in clk_pll_recalc_rate()
436 	val = val >> clk->refdiv_shift;  in clk_pll_recalc_rate()
437 	val &= ((1 << clk->refdiv_width) - 1);  in clk_pll_recalc_rate()
457 	void __iomem *base = data->base;  in hisi_clk_register_pll()
475 		p_clk->ctrl_reg1 = base + clks[i].ctrl_reg1;  in hisi_clk_register_pll()
476 		p_clk->frac_shift = clks[i].frac_shift;  in hisi_clk_register_pll()
477 		p_clk->frac_width = clks[i].frac_width;  in hisi_clk_register_pll()
478 		p_clk->postdiv1_shift = clks[i].postdiv1_shift;  in hisi_clk_register_pll()
479 		p_clk->postdiv1_width = clks[i].postdiv1_width;  in hisi_clk_register_pll()
480 		p_clk->postdiv2_shift = clks[i].postdiv2_shift;  in hisi_clk_register_pll()
481 		p_clk->postdiv2_width = clks[i].postdiv2_width;  in hisi_clk_register_pll()
483 		p_clk->ctrl_reg2 = base + clks[i].ctrl_reg2;  in hisi_clk_register_pll()
484 		p_clk->fbdiv_shift = clks[i].fbdiv_shift;  in hisi_clk_register_pll()
485 		p_clk->fbdiv_width = clks[i].fbdiv_width;  in hisi_clk_register_pll()
486 		p_clk->refdiv_shift = clks[i].refdiv_shift;  in hisi_clk_register_pll()
487 		p_clk->refdiv_width = clks[i].refdiv_width;  in hisi_clk_register_pll()
488 		p_clk->hw.init = &init;  in hisi_clk_register_pll()
490 		clk = clk_register(NULL, &p_clk->hw);  in hisi_clk_register_pll()
492 			dev_err(dev, "%s: failed to register clock %s\n",  in hisi_clk_register_pll()
497 		data->clk_data.clks[clks[i].id] = clk;  in hisi_clk_register_pll()
510 		return ERR_PTR(-ENOMEM);  in hi3559av100_clk_register()
518 			      ARRAY_SIZE(hi3559av100_pll_clks), clk_data, &pdev->dev);  in hi3559av100_clk_register()
530 	ret = of_clk_add_provider(pdev->dev.of_node,  in hi3559av100_clk_register()
531 				  of_clk_src_onecell_get, &clk_data->clk_data);  in hi3559av100_clk_register()
553 	of_clk_del_provider(pdev->dev.of_node);  in hi3559av100_clk_unregister()
556 				 ARRAY_SIZE(hi3559av100_gate_clks), crg->clk_data);  in hi3559av100_clk_unregister()
558 				ARRAY_SIZE(hi3559av100_mux_clks_crg), crg->clk_data);  in hi3559av100_clk_unregister()
560 				       ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), crg->clk_data);  in hi3559av100_clk_unregister()
706 		return ERR_PTR(-ENOMEM);  in hi3559av100_shub_clk_register()
728 	ret = of_clk_add_provider(pdev->dev.of_node,  in hi3559av100_shub_clk_register()
729 				  of_clk_src_onecell_get, &clk_data->clk_data);  in hi3559av100_shub_clk_register()
754 	of_clk_del_provider(pdev->dev.of_node);  in hi3559av100_shub_clk_unregister()
757 				 ARRAY_SIZE(hi3559av100_shub_gate_clks), crg->clk_data);  in hi3559av100_shub_clk_unregister()
759 				    ARRAY_SIZE(hi3559av100_shub_div_clks), crg->clk_data);  in hi3559av100_shub_clk_unregister()
761 				ARRAY_SIZE(hi3559av100_shub_mux_clks), crg->clk_data);  in hi3559av100_shub_clk_unregister()
763 				       ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), crg->clk_data);  in hi3559av100_shub_clk_unregister()
773 		.compatible = "hisilicon,hi3559av100-clock",
777 		.compatible = "hisilicon,hi3559av100-shub-clock",
788 	crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);  in hi3559av100_crg_probe()
790 		return -ENOMEM;  in hi3559av100_crg_probe()
792 	crg->funcs = of_device_get_match_data(&pdev->dev);  in hi3559av100_crg_probe()
793 	if (!crg->funcs)  in hi3559av100_crg_probe()
794 		return -ENOENT;  in hi3559av100_crg_probe()
796 	crg->rstc = hisi_reset_init(pdev);  in hi3559av100_crg_probe()
797 	if (!crg->rstc)  in hi3559av100_crg_probe()
798 		return -ENOMEM;  in hi3559av100_crg_probe()
800 	crg->clk_data = crg->funcs->register_clks(pdev);  in hi3559av100_crg_probe()
801 	if (IS_ERR(crg->clk_data)) {  in hi3559av100_crg_probe()
802 		hisi_reset_exit(crg->rstc);  in hi3559av100_crg_probe()
803 		return PTR_ERR(crg->clk_data);  in hi3559av100_crg_probe()
814 	hisi_reset_exit(crg->rstc);  in hi3559av100_crg_remove()
815 	crg->funcs->unregister_clks(pdev);  in hi3559av100_crg_remove()
822 		.name	= "hi3559av100-clock",
840 MODULE_DESCRIPTION("HiSilicon Hi3559AV100 CRG Driver");