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/linux/drivers/gpu/drm/arm/
H A Dhdlcd_drv.h3 * ARM HDLCD Controller register definition
27 static inline void hdlcd_write(struct hdlcd_drm_private *hdlcd, in hdlcd_write() argument
30 writel(value, hdlcd->mmio + reg); in hdlcd_write()
33 static inline u32 hdlcd_read(struct hdlcd_drm_private *hdlcd, unsigned int reg) in hdlcd_read() argument
35 return readl(hdlcd->mmio + reg); in hdlcd_read()
39 void hdlcd_set_scanout(struct hdlcd_drm_private *hdlcd);
H A DMakefile2 hdlcd-y := hdlcd_drv.o hdlcd_crtc.o
3 obj-$(CONFIG_DRM_HDLCD) += hdlcd.o
H A Dhdlcd_regs.h8 * ARM HDLCD Controller register definition
/linux/Documentation/devicetree/bindings/display/
H A Darm,hdlcd.yaml4 $id: http://devicetree.org/schemas/display/arm,hdlcd.yaml#
7 title: Arm HDLCD display controller
14 The Arm HDLCD is a display controller found on several development platforms
15 produced by ARM Ltd and in more modern of its Fast Models. The HDLCD is an
21 const: arm,hdlcd
62 hdlcd@2b000000 {
63 compatible = "arm,hdlcd";
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca5s.dts72 hdlcd@2a110000 {
73 compatible = "arm,hdlcd";
176 /* HDLCD */
H A Dvexpress-v2p-ca15-tc1.dts70 hdlcd@2b000000 {
71 compatible = "arm,hdlcd";
164 /* HDLCD PLL reference clock */
H A Dvexpress-v2p-ca15_a7.dts134 hdlcd@2b000000 {
135 compatible = "arm,hdlcd";
302 /* HDLCD PLL reference clock */
/linux/arch/arm64/boot/dts/arm/
H A Djuno-scmi.dtsi34 hdlcd@7ff50000 {
38 hdlcd@7ff60000 {
H A Djuno-base.dtsi867 hdlcd@7ff50000 {
868 compatible = "arm,hdlcd";
882 hdlcd@7ff60000 {
883 compatible = "arm,hdlcd";
/linux/
H A DMAINTAINERS2112 ARM HDLCD DRM DRIVER
2115 F: Documentation/devicetree/bindings/display/arm,hdlcd.yaml