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/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c35 { .name = "etnaviv-gpu,2d" },
43 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
45 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
49 *value = gpu->identity.model; in etnaviv_gpu_get_param()
53 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
57 *value = gpu->identity.features; in etnaviv_gpu_get_param()
61 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
65 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
69 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
73 *value = gpu in etnaviv_gpu_get_param()
179 etnaviv_gpu_reset_deassert(struct etnaviv_gpu * gpu) etnaviv_gpu_reset_deassert() argument
202 etnaviv_is_model_rev(struct etnaviv_gpu * gpu,u32 model,u32 revision) etnaviv_is_model_rev() argument
211 etnaviv_hw_specs(struct etnaviv_gpu * gpu) etnaviv_hw_specs() argument
361 etnaviv_hw_identify(struct etnaviv_gpu * gpu) etnaviv_hw_identify() argument
502 etnaviv_gpu_load_clock(struct etnaviv_gpu * gpu,u32 clock) etnaviv_gpu_load_clock() argument
509 etnaviv_gpu_update_clock(struct etnaviv_gpu * gpu) etnaviv_gpu_update_clock() argument
535 etnaviv_hw_reset(struct etnaviv_gpu * gpu) etnaviv_hw_reset() argument
636 etnaviv_gpu_enable_mlcg(struct etnaviv_gpu * gpu) etnaviv_gpu_enable_mlcg() argument
696 etnaviv_gpu_start_fe(struct etnaviv_gpu * gpu,u32 address,u16 prefetch) etnaviv_gpu_start_fe() argument
710 etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu * gpu,struct etnaviv_iommu_context * context) etnaviv_gpu_start_fe_idleloop() argument
731 etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu * gpu) etnaviv_gpu_setup_pulse_eater() argument
762 etnaviv_gpu_hw_init(struct etnaviv_gpu * gpu) etnaviv_gpu_hw_init() argument
817 etnaviv_gpu_init(struct etnaviv_gpu * gpu) etnaviv_gpu_init() argument
951 verify_dma(struct etnaviv_gpu * gpu,struct dma_debug * debug) verify_dma() argument
970 etnaviv_gpu_debugfs(struct etnaviv_gpu * gpu,struct seq_file * m) etnaviv_gpu_debugfs() argument
1135 struct etnaviv_gpu *gpu; global() member
1177 etnaviv_gpu_fence_alloc(struct etnaviv_gpu * gpu) etnaviv_gpu_fence_alloc() argument
1209 event_alloc(struct etnaviv_gpu * gpu,unsigned nr_events,unsigned int * events) event_alloc() argument
1262 event_free(struct etnaviv_gpu * gpu,unsigned int event) event_free() argument
1278 etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu * gpu,u32 id,struct drm_etnaviv_timespec * timeout) etnaviv_gpu_wait_fence_interruptible() argument
1325 etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu * gpu,struct etnaviv_gem_object * etnaviv_obj,struct drm_etnaviv_timespec * timeout) etnaviv_gpu_wait_obj_inactive() argument
1348 sync_point_perfmon_sample(struct etnaviv_gpu * gpu,struct etnaviv_event * event,unsigned int flags) sync_point_perfmon_sample() argument
1362 sync_point_perfmon_sample_pre(struct etnaviv_gpu * gpu,struct etnaviv_event * event) sync_point_perfmon_sample_pre() argument
1379 sync_point_perfmon_sample_post(struct etnaviv_gpu * gpu,struct etnaviv_event * event) sync_point_perfmon_sample_post() argument
1408 struct etnaviv_gpu *gpu = submit->gpu; etnaviv_gpu_submit() local
1474 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, sync_point_worker() local
1489 struct etnaviv_gpu *gpu = submit->gpu; etnaviv_gpu_recover_hang() local
1530 dump_mmu_fault(struct etnaviv_gpu * gpu) dump_mmu_fault() argument
1577 struct etnaviv_gpu *gpu = data; irq_handler() local
1644 etnaviv_gpu_clk_enable(struct etnaviv_gpu * gpu) etnaviv_gpu_clk_enable() argument
1676 etnaviv_gpu_clk_disable(struct etnaviv_gpu * gpu) etnaviv_gpu_clk_disable() argument
1686 etnaviv_gpu_wait_idle(struct etnaviv_gpu * gpu,unsigned int timeout_ms) etnaviv_gpu_wait_idle() argument
1707 etnaviv_gpu_hw_suspend(struct etnaviv_gpu * gpu) etnaviv_gpu_hw_suspend() argument
1728 etnaviv_gpu_hw_resume(struct etnaviv_gpu * gpu) etnaviv_gpu_hw_resume() argument
1757 struct etnaviv_gpu *gpu = cdev->devdata; etnaviv_gpu_cooling_get_cur_state() local
1768 struct etnaviv_gpu *gpu = cdev->devdata; etnaviv_gpu_cooling_set_cur_state() local
1790 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); etnaviv_gpu_bind() local
1844 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); etnaviv_gpu_unbind() local
1890 struct etnaviv_gpu *gpu; etnaviv_gpu_platform_probe() local
1975 struct etnaviv_gpu *gpu = dev_get_drvdata(&pdev->dev); etnaviv_gpu_platform_remove() local
1986 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); etnaviv_gpu_rpm_suspend() local
2012 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); etnaviv_gpu_rpm_resume() local
[all...]
H A Detnaviv_sched.c29 dev_dbg(submit->gpu->dev, "skipping bad job\n"); in etnaviv_sched_run_job()
38 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_sched_timedout_job() local
43 * If the GPU managed to complete this jobs fence, the timeout has in etnaviv_sched_timedout_job()
50 * If the GPU is still making forward progress on the front-end (which in etnaviv_sched_timedout_job()
54 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in etnaviv_sched_timedout_job()
55 change = dma_addr - gpu->hangcheck_dma_addr; in etnaviv_sched_timedout_job()
58 mutex_lock(&gpu->lock); in etnaviv_sched_timedout_job()
59 gpu_write(gpu, VIVS_MC_PROFILE_CONFIG0, in etnaviv_sched_timedout_job()
62 primid = gpu_read(gpu, VIVS_MC_PROFILE_FE_REA in etnaviv_sched_timedout_job()
109 struct etnaviv_gpu *gpu = submit->gpu; etnaviv_sched_push_job() local
143 etnaviv_sched_init(struct etnaviv_gpu * gpu) etnaviv_sched_init() argument
158 etnaviv_sched_fini(struct etnaviv_gpu * gpu) etnaviv_sched_fini() argument
[all...]
H A Detnaviv_gpu.h90 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
170 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() argument
172 writel(data, gpu->mmio + reg); in gpu_write()
175 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() argument
182 readl(gpu->mmio + reg); in gpu_read()
184 return readl(gpu->mmio + reg); in gpu_read()
187 static inline u32 gpu_fix_power_address(struct etnaviv_gpu *gpu, u32 reg) in gpu_fix_power_address() argument
190 if (gpu->identity.model == chipModel_GC300 && in gpu_fix_power_address()
191 gpu->identity.revision < 0x2000) in gpu_fix_power_address()
197 static inline void gpu_write_power(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write_power() argument
[all …]
H A Detnaviv_drv.c51 struct etnaviv_gpu *g = priv->gpu[i]; in load_gpu()
58 priv->gpu[i] = NULL; in load_gpu()
86 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_open() local
89 if (gpu) { in etnaviv_open()
90 sched = &gpu->sched; in etnaviv_open()
113 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_postclose() local
115 if (gpu) in etnaviv_postclose()
151 static int etnaviv_mmu_show(struct etnaviv_gpu *gpu, struct seq_file *m) in etnaviv_mmu_show() argument
156 seq_printf(m, "Active Objects (%s):\n", dev_name(gpu->dev)); in etnaviv_mmu_show()
159 * Lock the GPU to avoid a MMU context switch just now and elevate in etnaviv_mmu_show()
[all …]
H A Detnaviv_iommu_v2.c165 static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_nonsec() argument
172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
175 if (gpu->mmu_context) in etnaviv_iommuv2_restore_nonsec()
176 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_iommuv2_restore_nonsec()
177 gpu->mmu_context = etnaviv_iommu_context_get(context); in etnaviv_iommuv2_restore_nonsec()
179 prefetch = etnaviv_buffer_config_mmuv2(gpu, in etnaviv_iommuv2_restore_nonsec()
182 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_nonsec()
184 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_nonsec()
186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
189 static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_sec() argument
[all …]
/linux/drivers/gpu/drm/msm/
H A Dmsm_gpu.c26 static int enable_pwrrail(struct msm_gpu *gpu) in enable_pwrrail() argument
28 struct drm_device *dev = gpu->dev; in enable_pwrrail()
31 if (gpu->gpu_reg) { in enable_pwrrail()
32 ret = regulator_enable(gpu->gpu_reg); in enable_pwrrail()
39 if (gpu->gpu_cx) { in enable_pwrrail()
40 ret = regulator_enable(gpu->gpu_cx); in enable_pwrrail()
50 static int disable_pwrrail(struct msm_gpu *gpu) in disable_pwrrail() argument
52 if (gpu->gpu_cx) in disable_pwrrail()
53 regulator_disable(gpu->gpu_cx); in disable_pwrrail()
54 if (gpu in disable_pwrrail()
59 enable_clk(struct msm_gpu * gpu) enable_clk() argument
71 disable_clk(struct msm_gpu * gpu) disable_clk() argument
89 enable_axi(struct msm_gpu * gpu) enable_axi() argument
94 disable_axi(struct msm_gpu * gpu) disable_axi() argument
100 msm_gpu_pm_resume(struct msm_gpu * gpu) msm_gpu_pm_resume() argument
126 msm_gpu_pm_suspend(struct msm_gpu * gpu) msm_gpu_pm_suspend() argument
152 msm_gpu_show_fdinfo(struct msm_gpu * gpu,struct msm_context * ctx,struct drm_printer * p) msm_gpu_show_fdinfo() argument
160 msm_gpu_hw_init(struct msm_gpu * gpu) msm_gpu_hw_init() argument
182 struct msm_gpu *gpu = data; msm_gpu_devcoredump_read() local
216 struct msm_gpu *gpu = data; msm_gpu_devcoredump_free() local
364 msm_gpu_crashstate_capture(struct msm_gpu * gpu,struct msm_gem_submit * submit,struct msm_gpu_fault_info * fault_info,char * comm,char * cmd) msm_gpu_crashstate_capture() argument
409 msm_gpu_crashstate_capture(struct msm_gpu * gpu,struct msm_gem_submit * submit,struct msm_gpu_fault_info * fault_info,char * comm,char * cmd) msm_gpu_crashstate_capture() argument
466 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); recover_worker() local
589 msm_gpu_fault_crashstate_capture(struct msm_gpu * gpu,struct msm_gpu_fault_info * fault_info) msm_gpu_fault_crashstate_capture() argument
628 hangcheck_timer_reset(struct msm_gpu * gpu) hangcheck_timer_reset() argument
635 made_progress(struct msm_gpu * gpu,struct msm_ringbuffer * ring) made_progress() argument
652 struct msm_gpu *gpu = timer_container_of(gpu, t, hangcheck_timer); hangcheck_handler() local
689 update_hw_cntrs(struct msm_gpu * gpu,uint32_t ncntrs,uint32_t * cntrs) update_hw_cntrs() argument
709 update_sw_cntrs(struct msm_gpu * gpu) update_sw_cntrs() argument
733 msm_gpu_perfcntr_start(struct msm_gpu * gpu) msm_gpu_perfcntr_start() argument
749 msm_gpu_perfcntr_stop(struct msm_gpu * gpu) msm_gpu_perfcntr_stop() argument
756 msm_gpu_perfcntr_sample(struct msm_gpu * gpu,uint32_t * activetime,uint32_t * totaltime,uint32_t ncntrs,uint32_t * cntrs) msm_gpu_perfcntr_sample() argument
786 retire_submit(struct msm_gpu * gpu,struct msm_ringbuffer * ring,struct msm_gem_submit * submit) retire_submit() argument
835 retire_submits(struct msm_gpu * gpu) retire_submits() argument
870 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); retire_worker() local
876 msm_gpu_retire(struct msm_gpu * gpu) msm_gpu_retire() argument
888 msm_gpu_submit(struct msm_gpu * gpu,struct msm_gem_submit * submit) msm_gpu_submit() argument
935 struct msm_gpu *gpu = data; irq_handler() local
939 get_clocks(struct platform_device * pdev,struct msm_gpu * gpu) get_clocks() argument
961 msm_gpu_create_private_vm(struct msm_gpu * gpu,struct task_struct * task,bool kernel_managed) msm_gpu_create_private_vm() argument
986 msm_gpu_init(struct drm_device * drm,struct platform_device * pdev,struct msm_gpu * gpu,const struct msm_gpu_funcs * funcs,const char * name,struct msm_gpu_config * config) msm_gpu_init() argument
1134 msm_gpu_cleanup(struct msm_gpu * gpu) msm_gpu_cleanup() argument
[all...]
H A Dmsm_gpu.h50 int (*get_param)(struct msm_gpu *gpu, struct msm_context *ctx,
52 int (*set_param)(struct msm_gpu *gpu, struct msm_context *ctx,
54 int (*hw_init)(struct msm_gpu *gpu);
59 int (*ucode_load)(struct msm_gpu *gpu);
61 int (*pm_suspend)(struct msm_gpu *gpu);
62 int (*pm_resume)(struct msm_gpu *gpu);
63 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
64 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
66 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
67 void (*recover)(struct msm_gpu *gpu);
291 adreno_smmu_has_prr(struct msm_gpu * gpu) adreno_smmu_has_prr() argument
309 msm_gpu_active(struct msm_gpu * gpu) msm_gpu_active() argument
490 msm_gpu_convert_priority(struct msm_gpu * gpu,int prio,unsigned * ring_nr,enum drm_sched_priority * sched_prio) msm_gpu_convert_priority() argument
595 gpu_write(struct msm_gpu * gpu,u32 reg,u32 data) gpu_write() argument
601 gpu_read(struct msm_gpu * gpu,u32 reg) gpu_read() argument
607 gpu_rmw(struct msm_gpu * gpu,u32 reg,u32 mask,u32 or) gpu_rmw() argument
613 gpu_read64(struct msm_gpu * gpu,u32 reg) gpu_read64() argument
639 gpu_write64(struct msm_gpu * gpu,u32 reg,u64 val) gpu_write64() argument
721 msm_gpu_crashstate_get(struct msm_gpu * gpu) msm_gpu_crashstate_get() argument
737 msm_gpu_crashstate_put(struct msm_gpu * gpu) msm_gpu_crashstate_put() argument
755 check_apriv(gpu,flags) global() argument
[all...]
H A Dmsm_ringbuffer.c18 struct msm_gpu *gpu = submit->gpu; in msm_job_run() local
19 struct drm_device *dev = gpu->dev; in msm_job_run()
38 mutex_lock(&gpu->lock); in msm_job_run()
43 msm_gpu_submit(gpu, submit); in msm_job_run()
47 mutex_unlock(&gpu->lock); in msm_job_run()
65 struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, in msm_ringbuffer_new() argument
72 .dev = gpu->dev->dev, in msm_ringbuffer_new()
87 ring->gpu = gpu; in msm_ringbuffer_new()
[all...]
H A Dmsm_debugfs.c24 * GPU Snapshot:
37 struct msm_gpu *gpu = priv->gpu; in msm_gpu_show() local
40 ret = mutex_lock_interruptible(&gpu->lock); in msm_gpu_show()
44 drm_printf(&p, "%s Status:\n", gpu->name); in msm_gpu_show()
45 gpu->funcs->show(gpu, show_priv->state, &p); in msm_gpu_show()
47 mutex_unlock(&gpu->lock); in msm_gpu_show()
57 struct msm_gpu *gpu = priv->gpu; in msm_gpu_release() local
72 struct msm_gpu *gpu = priv->gpu; msm_gpu_open() local
[all...]
/linux/drivers/gpu/drm/msm/adreno/
H A Da8xx_gpu.c19 static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice) in a8xx_aperture_slice_set() argument
21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a8xx_aperture_slice_set()
30 gpu_write(gpu, REG_A8XX_CP_APERTURE_CNTL_HOST, val); in a8xx_aperture_slice_set()
35 static void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) in a8xx_aperture_acquire() argument
37 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a8xx_aperture_acquire()
42 a8xx_aperture_slice_set(gpu, pipe, 0); in a8xx_aperture_acquire()
45 static void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags) in a8xx_aperture_release() argument
47 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a8xx_aperture_release()
53 static void a8xx_aperture_clear(struct msm_gpu *gpu) in a8xx_aperture_clear() argument
57 a8xx_aperture_acquire(gpu, PIPE_NON in a8xx_aperture_clear()
61 a8xx_write_pipe(struct msm_gpu * gpu,enum adreno_pipe pipe,u32 offset,u32 data) a8xx_write_pipe() argument
70 a8xx_read_pipe_slice(struct msm_gpu * gpu,enum adreno_pipe pipe,u32 slice,u32 offset) a8xx_read_pipe_slice() argument
85 a8xx_gpu_get_slice_info(struct msm_gpu * gpu) a8xx_gpu_get_slice_info() argument
130 _a8xx_check_idle(struct msm_gpu * gpu) _a8xx_check_idle() argument
148 a8xx_idle(struct msm_gpu * gpu,struct msm_ringbuffer * ring) a8xx_idle() argument
168 a8xx_flush(struct msm_gpu * gpu,struct msm_ringbuffer * ring) a8xx_flush() argument
196 a8xx_set_hwcg(struct msm_gpu * gpu,bool state) a8xx_set_hwcg() argument
235 a8xx_set_cp_protect(struct msm_gpu * gpu) a8xx_set_cp_protect() argument
274 a8xx_set_ubwc_config(struct msm_gpu * gpu) a8xx_set_ubwc_config() argument
368 a8xx_nonctxt_config(struct msm_gpu * gpu,u32 * gmem_protect) a8xx_nonctxt_config() argument
399 a8xx_patch_pwrup_reglist(struct msm_gpu * gpu) a8xx_patch_pwrup_reglist() argument
476 a8xx_preempt_start(struct msm_gpu * gpu) a8xx_preempt_start() argument
504 a8xx_cp_init(struct msm_gpu * gpu) a8xx_cp_init() argument
632 hw_init(struct msm_gpu * gpu) hw_init() argument
861 a8xx_hw_init(struct msm_gpu * gpu) a8xx_hw_init() argument
874 a8xx_dump(struct msm_gpu * gpu) a8xx_dump() argument
880 a8xx_recover(struct msm_gpu * gpu) a8xx_recover() argument
943 a8xx_uche_fault_block(struct msm_gpu * gpu,u32 mid) a8xx_uche_fault_block() argument
982 a8xx_fault_block(struct msm_gpu * gpu,u32 id) a8xx_fault_block() argument
1011 struct msm_gpu *gpu = arg; a8xx_fault_handler() local
1028 a8xx_cp_hw_err_irq(struct msm_gpu * gpu) a8xx_cp_hw_err_irq() argument
1096 gpu_periph_read(struct msm_gpu * gpu,u32 dbg_offset) gpu_periph_read() argument
1103 gpu_periph_read64(struct msm_gpu * gpu,u32 dbg_offset) gpu_periph_read64() argument
1126 a8xx_fault_detect_irq(struct msm_gpu * gpu) a8xx_fault_detect_irq() argument
1192 a8xx_sw_fuse_violation_irq(struct msm_gpu * gpu) a8xx_sw_fuse_violation_irq() argument
1213 a8xx_irq(struct msm_gpu * gpu) a8xx_irq() argument
1267 struct msm_gpu *gpu = &adreno_gpu->base; a8xx_llc_activate() local
1299 struct msm_gpu *gpu = &adreno_gpu->base; a8xx_bus_clear_pending_transactions() local
1321 a8xx_gmu_get_timestamp(struct msm_gpu * gpu) a8xx_gmu_get_timestamp() argument
1336 a8xx_gpu_busy(struct msm_gpu * gpu,unsigned long * out_sample_rate) a8xx_gpu_busy() argument
1352 a8xx_progress(struct msm_gpu * gpu,struct msm_ringbuffer * ring) a8xx_progress() argument
[all...]
H A Da3xx_gpu.c28 static void a3xx_dump(struct msm_gpu *gpu);
29 static bool a3xx_idle(struct msm_gpu *gpu);
31 static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a3xx_submit() argument
69 /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */ in a3xx_submit()
82 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_submit()
85 static bool a3xx_me_init(struct msm_gpu *gpu) in a3xx_me_init() argument
87 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init()
108 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_me_init()
109 return a3xx_idle(gpu); in a3xx_me_init()
112 static int a3xx_hw_init(struct msm_gpu *gpu) in a3xx_hw_init() argument
366 a3xx_recover(struct msm_gpu * gpu) a3xx_recover() argument
387 a3xx_destroy(struct msm_gpu * gpu) a3xx_destroy() argument
401 a3xx_idle(struct msm_gpu * gpu) a3xx_idle() argument
419 a3xx_irq(struct msm_gpu * gpu) a3xx_irq() argument
474 a3xx_dump(struct msm_gpu * gpu) a3xx_dump() argument
481 a3xx_gpu_state_get(struct msm_gpu * gpu) a3xx_gpu_state_get() argument
495 a3xx_gpu_busy(struct msm_gpu * gpu,unsigned long * out_sample_rate) a3xx_gpu_busy() argument
505 a3xx_get_rptr(struct msm_gpu * gpu,struct msm_ringbuffer * ring) a3xx_get_rptr() argument
522 struct msm_gpu *gpu; a3xx_gpu_init() local
[all...]
H A Da6xx_gpu.c19 static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu) in a6xx_gmu_get_timestamp()
21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gmu_get_timestamp()
34 static bool fence_status_check(struct msm_gpu *gpu, u32 offset, u32 value, u32 status, u32 mask) in fence_status_check()
43 gpu_write(gpu, offset, value); in fence_status_check()
55 struct msm_gpu *gpu = &adreno_gpu->base; in fenced_write()
59 gpu_write(gpu, offset, value); in fenced_write()
71 fence_status_check(gpu, offset, value, status, mask), 0, 1000)) in fenced_write()
75 gpu_write(gpu, offset, value); in fenced_write()
79 fence_status_check(gpu, offset, value, status, mask), 0, 1000)) { in fenced_write()
82 * warning will allow gpu t in fenced_write()
18 a6xx_gmu_get_timestamp(struct msm_gpu * gpu) a6xx_gmu_get_timestamp() argument
33 fence_status_check(struct msm_gpu * gpu,u32 offset,u32 value,u32 status,u32 mask) fence_status_check() argument
54 struct msm_gpu *gpu = &adreno_gpu->base; fenced_write() local
111 _a6xx_check_idle(struct msm_gpu * gpu) _a6xx_check_idle() argument
129 a6xx_idle(struct msm_gpu * gpu,struct msm_ringbuffer * ring) a6xx_idle() argument
148 update_shadow_rptr(struct msm_gpu * gpu,struct msm_ringbuffer * ring) update_shadow_rptr() argument
161 a6xx_flush(struct msm_gpu * gpu,struct msm_ringbuffer * ring) a6xx_flush() argument
329 a6xx_submit(struct msm_gpu * gpu,struct msm_gem_submit * submit) a6xx_submit() argument
453 a7xx_submit(struct msm_gpu * gpu,struct msm_gem_submit * submit) a7xx_submit() argument
629 a6xx_set_hwcg(struct msm_gpu * gpu,bool state) a6xx_set_hwcg() argument
711 a6xx_set_cp_protect(struct msm_gpu * gpu) a6xx_set_cp_protect() argument
736 a6xx_calc_ubwc_config(struct adreno_gpu * gpu) a6xx_calc_ubwc_config() argument
812 a6xx_set_ubwc_config(struct msm_gpu * gpu) a6xx_set_ubwc_config() argument
874 a7xx_patch_pwrup_reglist(struct msm_gpu * gpu) a7xx_patch_pwrup_reglist() argument
945 a7xx_preempt_start(struct msm_gpu * gpu) a7xx_preempt_start() argument
973 a6xx_cp_init(struct msm_gpu * gpu) a6xx_cp_init() argument
1002 a7xx_cp_init(struct msm_gpu * gpu) a7xx_cp_init() argument
1061 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_ucode_check_version() local
1124 a6xx_ucode_load(struct msm_gpu * gpu) a6xx_ucode_load() argument
1201 a6xx_zap_shader_init(struct msm_gpu * gpu) a6xx_zap_shader_init() argument
1251 hw_init(struct msm_gpu * gpu) hw_init() argument
1619 a6xx_hw_init(struct msm_gpu * gpu) a6xx_hw_init() argument
1632 a6xx_dump(struct msm_gpu * gpu) a6xx_dump() argument
1639 a6xx_recover(struct msm_gpu * gpu) a6xx_recover() argument
1715 a6xx_uche_fault_block(struct msm_gpu * gpu,u32 mid) a6xx_uche_fault_block() argument
1812 a6xx_fault_block(struct msm_gpu * gpu,u32 id) a6xx_fault_block() argument
1832 struct msm_gpu *gpu = arg; a6xx_fault_handler() local
1849 a6xx_cp_hw_err_irq(struct msm_gpu * gpu) a6xx_cp_hw_err_irq() argument
1891 a6xx_fault_detect_irq(struct msm_gpu * gpu) a6xx_fault_detect_irq() argument
1924 a7xx_sw_fuse_violation_irq(struct msm_gpu * gpu) a7xx_sw_fuse_violation_irq() argument
1945 a6xx_gpu_keepalive_vote(struct msm_gpu * gpu,bool on) a6xx_gpu_keepalive_vote() argument
1956 irq_poll_fence(struct msm_gpu * gpu) irq_poll_fence() argument
1978 a6xx_irq(struct msm_gpu * gpu) a6xx_irq() argument
2039 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_llc_activate() local
2099 struct msm_gpu *gpu = &adreno_gpu->base; a7xx_llc_activate() local
2173 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_bus_clear_pending_transactions() local
2208 a6xx_gpu_sw_reset(struct msm_gpu * gpu,bool assert) a6xx_gpu_sw_reset() argument
2224 a6xx_gmu_pm_resume(struct msm_gpu * gpu) a6xx_gmu_pm_resume() argument
2252 a6xx_pm_resume(struct msm_gpu * gpu) a6xx_pm_resume() argument
2311 a6xx_gmu_pm_suspend(struct msm_gpu * gpu) a6xx_gmu_pm_suspend() argument
2338 a6xx_pm_suspend(struct msm_gpu * gpu) a6xx_pm_suspend() argument
2377 a6xx_get_timestamp(struct msm_gpu * gpu) a6xx_get_timestamp() argument
2382 a6xx_active_ring(struct msm_gpu * gpu) a6xx_active_ring() argument
2390 a6xx_destroy(struct msm_gpu * gpu) a6xx_destroy() argument
2419 a6xx_gpu_busy(struct msm_gpu * gpu,unsigned long * out_sample_rate) a6xx_gpu_busy() argument
2435 a6xx_gpu_set_freq(struct msm_gpu * gpu,struct dev_pm_opp * opp,bool suspended) a6xx_gpu_set_freq() argument
2447 a6xx_create_vm(struct msm_gpu * gpu,struct platform_device * pdev) a6xx_create_vm() argument
2465 a6xx_create_private_vm(struct msm_gpu * gpu,bool kernel_managed) a6xx_create_private_vm() argument
2478 a6xx_get_rptr(struct msm_gpu * gpu,struct msm_ringbuffer * ring) a6xx_get_rptr() argument
2496 a6xx_progress(struct msm_gpu * gpu,struct msm_ringbuffer * ring) a6xx_progress() argument
2626 struct msm_gpu *gpu; a6xx_gpu_init() local
[all...]
H A Dadreno_device.c16 MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");
24 MODULE_PARM_DESC(disable_acd, "Forcefully disable GPU ACD");
28 MODULE_PARM_DESC(no_gpu, "Disable GPU driver register (0=enable GPU driver register (default), 1=skip GPU driver register");
51 /* identify gpu: */ in adreno_info()
72 struct msm_gpu *gpu = NULL; in adreno_load_gpu() local
77 gpu = dev_to_gpu(&pdev->dev); in adreno_load_gpu()
79 if (!gpu) { in adreno_load_gpu()
80 dev_err_once(dev->dev, "no GPU devic in adreno_load_gpu()
216 struct msm_gpu *gpu; adreno_bind() local
258 struct msm_gpu *gpu = dev_to_gpu(dev); adreno_unbind() local
309 struct msm_gpu *gpu = dev_to_gpu(dev); adreno_runtime_resume() local
316 struct msm_gpu *gpu = dev_to_gpu(dev); adreno_runtime_suspend() local
328 suspend_scheduler(struct msm_gpu * gpu) suspend_scheduler() argument
350 resume_scheduler(struct msm_gpu * gpu) resume_scheduler() argument
363 struct msm_gpu *gpu = dev_to_gpu(dev); adreno_system_suspend() local
390 struct msm_gpu *gpu = dev_to_gpu(dev); adreno_system_resume() local
[all...]
H A Da2xx_gpu.c10 static void a2xx_dump(struct msm_gpu *gpu);
11 static bool a2xx_idle(struct msm_gpu *gpu);
13 static void a2xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a2xx_submit() argument
51 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_submit()
54 static bool a2xx_me_init(struct msm_gpu *gpu) in a2xx_me_init() argument
56 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a2xx_me_init()
58 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
107 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_me_init()
108 return a2xx_idle(gpu); in a2xx_me_init()
111 static int a2xx_hw_init(struct msm_gpu *gpu) in a2xx_hw_init() argument
269 a2xx_recover(struct msm_gpu * gpu) a2xx_recover() argument
290 a2xx_destroy(struct msm_gpu * gpu) a2xx_destroy() argument
302 a2xx_idle(struct msm_gpu * gpu) a2xx_idle() argument
320 a2xx_irq(struct msm_gpu * gpu) a2xx_irq() argument
451 a2xx_dump(struct msm_gpu * gpu) a2xx_dump() argument
458 a2xx_gpu_state_get(struct msm_gpu * gpu) a2xx_gpu_state_get() argument
473 a2xx_create_vm(struct msm_gpu * gpu,struct platform_device * pdev) a2xx_create_vm() argument
486 a2xx_get_rptr(struct msm_gpu * gpu,struct msm_ringbuffer * ring) a2xx_get_rptr() argument
500 struct msm_gpu *gpu; a2xx_gpu_init() local
[all...]
H A Da5xx_preempt.c25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
58 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in get_next_ring()
63 for (i = 0; i < gpu->nr_rings; i++) { in get_next_ring()
65 struct msm_ringbuffer *ring = gpu->rb[i]; in get_next_ring()
68 empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); in get_next_ring()
84 struct msm_gpu *gpu = &a5xx_gpu->base.base; in a5xx_preempt_timer() local
[all …]
H A Dadreno_gpu.c25 MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space");
30 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, in zap_shader_load_mdt() argument
33 struct device *dev = &gpu->pdev->dev; in zap_shader_load_mdt()
78 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev); in zap_shader_load_mdt()
83 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); in zap_shader_load_mdt()
133 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) { in zap_shader_load_mdt()
169 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) in adreno_zap_shader_load() argument
171 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_zap_shader_load()
172 struct platform_device *pdev = gpu->pdev; in adreno_zap_shader_load()
184 return zap_shader_load_mdt(gpu, adreno_gp in adreno_zap_shader_load()
188 adreno_create_vm(struct msm_gpu * gpu,struct platform_device * pdev) adreno_create_vm() argument
195 adreno_iommu_create_vm(struct msm_gpu * gpu,struct platform_device * pdev,unsigned long quirks) adreno_iommu_create_vm() argument
229 adreno_private_vm_size(struct msm_gpu * gpu) adreno_private_vm_size() argument
257 struct msm_gpu *gpu = &adreno_gpu->base; adreno_check_and_reenable_stall() local
283 adreno_fault_handler(struct msm_gpu * gpu,unsigned long iova,int flags,struct adreno_smmu_fault_info * info,const char * block,u32 scratch[4]) adreno_fault_handler() argument
359 adreno_get_param(struct msm_gpu * gpu,struct msm_context * ctx,uint32_t param,uint64_t * value,uint32_t * len) adreno_get_param() argument
459 adreno_set_param(struct msm_gpu * gpu,struct msm_context * ctx,uint32_t param,uint64_t value,uint32_t len) adreno_set_param() argument
635 adreno_fw_create_bo(struct msm_gpu * gpu,const struct firmware * fw,u64 * iova) adreno_fw_create_bo() argument
654 adreno_hw_init(struct msm_gpu * gpu) adreno_hw_init() argument
696 struct msm_gpu *gpu = &adreno_gpu->base; get_rptr() local
701 adreno_active_ring(struct msm_gpu * gpu) adreno_active_ring() argument
706 adreno_recover(struct msm_gpu * gpu) adreno_recover() argument
724 adreno_flush(struct msm_gpu * gpu,struct msm_ringbuffer * ring,u32 reg) adreno_flush() argument
744 adreno_idle(struct msm_gpu * gpu,struct msm_ringbuffer * ring) adreno_idle() argument
760 adreno_gpu_state_get(struct msm_gpu * gpu,struct msm_gpu_state * state) adreno_gpu_state_get() argument
938 adreno_show(struct msm_gpu * gpu,struct msm_gpu_state * state,struct drm_printer * p) adreno_show() argument
1036 adreno_dump_info(struct msm_gpu * gpu) adreno_dump_info() argument
1058 adreno_dump(struct msm_gpu * gpu) adreno_dump() argument
1099 adreno_get_pwrlevels(struct device * dev,struct msm_gpu * gpu) adreno_get_pwrlevels() argument
1193 struct msm_gpu *gpu = &adreno_gpu->base; adreno_gpu_init() local
1249 struct msm_gpu *gpu = &adreno_gpu->base; adreno_gpu_cleanup() local
[all...]
/linux/sound/hda/codecs/hdmi/
H A Dnvhdmi.c145 HDA_CODEC_ID_MODEL(0x10de0008, "GPU 08 HDMI/DP", MODEL_LEGACY),
146 HDA_CODEC_ID_MODEL(0x10de0009, "GPU 09 HDMI/DP", MODEL_LEGACY),
147 HDA_CODEC_ID_MODEL(0x10de000a, "GPU 0a HDMI/DP", MODEL_LEGACY),
148 HDA_CODEC_ID_MODEL(0x10de000b, "GPU 0b HDMI/DP", MODEL_LEGACY),
150 HDA_CODEC_ID_MODEL(0x10de000d, "GPU 0d HDMI/DP", MODEL_LEGACY),
151 HDA_CODEC_ID_MODEL(0x10de0010, "GPU 10 HDMI/DP", MODEL_LEGACY),
152 HDA_CODEC_ID_MODEL(0x10de0011, "GPU 11 HDMI/DP", MODEL_LEGACY),
153 HDA_CODEC_ID_MODEL(0x10de0012, "GPU 12 HDMI/DP", MODEL_LEGACY),
154 HDA_CODEC_ID_MODEL(0x10de0013, "GPU 13 HDMI/DP", MODEL_LEGACY),
155 HDA_CODEC_ID_MODEL(0x10de0014, "GPU 14 HDMI/DP", MODEL_LEGACY),
[all …]
/linux/drivers/gpu/drm/
H A Ddrm_gpusvm.c25 * GPU Shared Virtual Memory (GPU SVM) layer for the Direct Rendering Manager (DRM)
27 * between the CPU and GPU. It enables efficient data exchange and processing
28 * for GPU-accelerated applications by allowing memory sharing and
29 * synchronization between the CPU's and GPU's virtual address spaces.
31 * Key GPU SVM Components:
34 * Used for tracking memory intervals and notifying the GPU of changes,
35 * notifiers are sized based on a GPU SVM initialization parameter, with a
38 * tracked within a GPU SVM Red-BlacK tree and list and are dynamically
42 * Represent memory ranges mapped in a DRM device and managed by GPU SV
[all...]
/linux/Documentation/gpu/rfc/
H A Dgpusvm.rst4 GPU SVM Section
25 * Eviction is defined as migrating data from the GPU back to the
26 CPU without a virtual address to free up GPU memory.
32 * GPU page table invalidation, which requires a GPU virtual address, is
33 handled via the notifier that has access to the GPU virtual address.
34 * GPU fault side
36 and should strive to take mmap_read lock only in GPU SVM layer.
37 * Big retry loop to handle all races with the mmu notifier under the gpu
47 migration policy requiring GPU access to occur in GPU memory.
49 While no current user (Xe) of GPU SVM has such a policy, it is likely
[all …]
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_topology.c108 return top_dev->gpu; in kfd_device_by_id()
260 if (iolink->gpu && kfd_devcgroup_check_permission(iolink->gpu)) in iolink_show()
302 if (mem->gpu && kfd_devcgroup_check_permission(mem->gpu)) in mem_show()
334 if (cache->gpu && kfd_devcgroup_check_permission(cache->gpu)) in kfd_cache_show()
416 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu)) in node_show()
425 if (dev->gpu in node_show()
1085 kfd_generate_gpu_id(struct kfd_node * gpu) kfd_generate_gpu_id() argument
1144 kfd_assign_gpu(struct kfd_node * gpu) kfd_assign_gpu() argument
1275 struct kfd_node *gpu = outbound_link->gpu; kfd_set_recommended_sdma_engines() local
1868 kfd_topology_add_device_locked(struct kfd_node * gpu,struct kfd_topology_device ** dev) kfd_topology_add_device_locked() argument
2038 kfd_topology_add_device(struct kfd_node * gpu) kfd_topology_add_device() argument
2266 kfd_topology_remove_device(struct kfd_node * gpu) kfd_topology_remove_device() argument
[all...]
/linux/Documentation/devicetree/bindings/gpu/
H A Dimg,powervr-sgx.yaml6 $id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml#
19 - ti,omap3430-gpu # Rev 121
20 - ti,omap3630-gpu # Rev 125
24 - ingenic,jz4780-gpu # Rev 130
25 - ti,omap4430-gpu # Rev 120
29 - allwinner,sun6i-a31-gpu # MP2 Rev 115
30 - ti,omap4470-gpu # MP1 Rev 112
31 - ti,omap5432-gpu # MP2 Rev 105
32 - ti,am5728-gpu # MP2 Rev 116
33 - ti,am6548-gpu # MP1 Rev 117
[all …]
H A Dimg,powervr-rogue.yaml5 $id: http://devicetree.org/schemas/gpu/img,powervr-rogue.yaml#
18 - renesas,r8a7796-gpu
19 - renesas,r8a77961-gpu
24 - renesas,r8a77965-gpu
25 - renesas,r8a779a0-gpu
30 - ti,am62-gpu
38 - thead,th1520-gpu
43 - ti,am62p-gpu
44 - ti,j721s2-gpu
49 # before the more specific GPU identifiers were used.
[all …]
/linux/Documentation/gpu/
H A Ddrm-kms.rst164 .. kernel-doc:: drivers/gpu/drm/drm_mode_config.c
196 .. kernel-doc:: drivers/gpu/drm/drm_mode_object.c
293 .. kernel-doc:: drivers/gpu/drm/drm_atomic.c
302 .. kernel-doc:: drivers/gpu/drm/drm_atomic.c
308 .. kernel-doc:: drivers/gpu/drm/drm_atomic_uapi.c
311 .. kernel-doc:: drivers/gpu/drm/drm_atomic_uapi.c
317 .. kernel-doc:: drivers/gpu/drm/drm_crtc.c
326 .. kernel-doc:: drivers/gpu/drm/drm_crtc.c
332 .. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
341 .. kernel-doc:: drivers/gpu/dr
[all...]
H A Dvc4.rst5 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_drv.c
18 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_crtc.c
24 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_hvs.c
30 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_plane.c
36 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_hdmi.c
42 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_dsi.c
48 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_dpi.c
54 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_vec.c
69 --kunitconfig=drivers/gpu/drm/vc4/tests/.kunitconfig \
81 GPU buffer object (BO) management
[all …]
/linux/Documentation/driver-api/
H A Dedac.rst116 Several stacks of HBM chips connect to the CPU or GPU through an ultra-fast
196 GPU nodes can be accessed the same way as the data fabric on CPU nodes.
199 and each GPU data fabric contains four Unified Memory Controllers (UMC).
207 Memory controllers on AMD GPU nodes can be represented in EDAC thusly:
209 GPU DF / GPU Node -> EDAC MC
210 GPU UMC -> EDAC CSROW
211 GPU UMC channel -> EDAC CHANNEL
218 - The CPU UMC (Unified Memory Controller) is mostly the same as the GPU UMC.
224 - GPU UMCs use 1 chip select, So UMC = EDAC CSROW.
225 - GPU UMCs use 8 channels, So UMC channel = EDAC channel.
[all …]

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