49 	int (*get_param)(struct msm_gpu *gpu, struct msm_context *ctx,
51 	int (*set_param)(struct msm_gpu *gpu, struct msm_context *ctx,
53 	int (*hw_init)(struct msm_gpu *gpu);
58 	int (*ucode_load)(struct msm_gpu *gpu);
60 	int (*pm_suspend)(struct msm_gpu *gpu);
61 	int (*pm_resume)(struct msm_gpu *gpu);
62 	void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
63 	void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
65 	struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
66 	void (*recover)(struct msm_gpu *gpu);
67 	void (*destroy)(struct msm_gpu *gpu);
69 	/* show GPU status in debugfs: */
70 	void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
73 	void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
76 	u64 (*gpu_busy)(struct msm_gpu *gpu, unsigned long *out_sample_rate);
77 	struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
79 	unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
81 	void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp,
83 	struct drm_gpuvm *(*create_vm)(struct msm_gpu *gpu, struct platform_device *pdev);
84 	struct drm_gpuvm *(*create_private_vm)(struct msm_gpu *gpu, bool kernel_managed);
85 	uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
88 	 * progress: Has the GPU made progress?
90 	 * Return true if GPU position in cmdstream has advanced (or changed)
94 	bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
95 	void (*sysprof_setup)(struct msm_gpu *gpu);
128 	 * Shadow frequency used while the GPU is idle.  From the PoV of
130 	 * adjust frequency while the GPU is idle, but we use this shadow
131 	 * value as the GPU is actually clamped to minimum frequency while
208 	 * General lock for serializing all the gpu things.
228 	/* does gpu need hw_init? */
232 	 * global_faults: number of GPU hangs not attributed to a particular
257 	/* work for handling GPU recovery: */
303 adreno_smmu_has_prr(struct msm_gpu *gpu)  in adreno_smmu_has_prr()  argument
305 	struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(&gpu->pdev->dev);  in adreno_smmu_has_prr()
321 static inline bool msm_gpu_active(struct msm_gpu *gpu)  in msm_gpu_active()  argument
325 	for (i = 0; i < gpu->nr_rings; i++) {  in msm_gpu_active()
326 		struct msm_ringbuffer *ring = gpu->rb[i];  in msm_gpu_active()
349  * The number of priority levels provided by drm gpu scheduler.  The
392 	 * The per-process GPU address-space.  Do not access directly, use
444 	 * The total (cumulative) elapsed time GPU was busy with rendering
452 	 * The total (cumulative) GPU cycles elapsed attributed to this
500  * @gpu:        the gpu instance
503  * @sched_prio: [out] the gpu scheduler priority level which the userspace
522 static inline int msm_gpu_convert_priority(struct msm_gpu *gpu, int prio,  in msm_gpu_convert_priority()  argument
534 	if (rn >= gpu->nr_rings)  in msm_gpu_convert_priority()
554  * @faults:    the number of GPU hangs associated with this submitqueue
627 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)  in gpu_write()  argument
630 	writel(data, gpu->mmio + (reg << 2));  in gpu_write()
633 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)  in gpu_read()  argument
636 	return readl(gpu->mmio + (reg << 2));  in gpu_read()
639 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)  in gpu_rmw()  argument
642 	msm_rmw(gpu->mmio + (reg << 2), mask, or);  in gpu_rmw()
645 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 reg)  in gpu_read64()  argument
651 	 * not quad word aligned and 2) the GPU hardware designers have a bit  in gpu_read64()
653 	 * spins. The longer a GPU family goes the higher the chance that  in gpu_read64()
664 	val = (u64) readl(gpu->mmio + (reg << 2));  in gpu_read64()
666 	val |= ((u64) readl(gpu->mmio + ((reg + 1) << 2)) << 32);  in gpu_read64()
671 static inline void gpu_write64(struct msm_gpu *gpu, u32 reg, u64 val)  in gpu_write64()  argument
675 	writel(lower_32_bits(val), gpu->mmio + (reg << 2));  in gpu_write64()
677 	writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));  in gpu_write64()
680 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
681 int msm_gpu_pm_resume(struct msm_gpu *gpu);
683 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_context *ctx,
699 int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sysprof);
714 void msm_devfreq_init(struct msm_gpu *gpu);
715 void msm_devfreq_cleanup(struct msm_gpu *gpu);
716 void msm_devfreq_resume(struct msm_gpu *gpu);
717 void msm_devfreq_suspend(struct msm_gpu *gpu);
718 void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor);
719 void msm_devfreq_active(struct msm_gpu *gpu);
720 void msm_devfreq_idle(struct msm_gpu *gpu);
722 int msm_gpu_hw_init(struct msm_gpu *gpu);
724 void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
725 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
726 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
729 void msm_gpu_retire(struct msm_gpu *gpu);
730 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit);
733 		struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
737 msm_gpu_create_private_vm(struct msm_gpu *gpu, struct task_struct *task,
740 void msm_gpu_cleanup(struct msm_gpu *gpu);
753 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)  in msm_gpu_crashstate_get()  argument
757 	mutex_lock(&gpu->lock);  in msm_gpu_crashstate_get()
759 	if (gpu->crashstate) {  in msm_gpu_crashstate_get()
760 		kref_get(&gpu->crashstate->ref);  in msm_gpu_crashstate_get()
761 		state = gpu->crashstate;  in msm_gpu_crashstate_get()
764 	mutex_unlock(&gpu->lock);  in msm_gpu_crashstate_get()
769 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)  in msm_gpu_crashstate_put()  argument
771 	mutex_lock(&gpu->lock);  in msm_gpu_crashstate_put()
773 	if (gpu->crashstate) {  in msm_gpu_crashstate_put()
774 		if (gpu->funcs->gpu_state_put(gpu->crashstate))  in msm_gpu_crashstate_put()
775 			gpu->crashstate = NULL;  in msm_gpu_crashstate_put()
778 	mutex_unlock(&gpu->lock);  in msm_gpu_crashstate_put()
781 void msm_gpu_fault_crashstate_capture(struct msm_gpu *gpu, struct msm_gpu_fault_info *fault_info);
787 #define check_apriv(gpu, flags) \  argument
788 	(((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))