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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dqcom,pmic-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,pmic-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PMIC GPIO block
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 This binding describes the GPIO block(s) found in the 8xxx series of
19 - enum:
20 - qcom,pm2250-gpio
21 - qcom,pm660-gpio
[all …]
H A Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
24 mpp0 0 gpio, nand(io2), spi(cs)
28 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
32 mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
[all …]
H A Dmarvell,armada-37xx-pinctrl.txt1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
6 Inside this set of register the gpio latch allows exposing some
11 GPIO and pin controller:
12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
[all …]
H A Dmarvell,armada-xp-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl"
9 - reg: register specifier of MPP registers
21 mpp0 0 gpio, ge0(txclkout), lcd(d0)
22 mpp1 1 gpio, ge0(txd0), lcd(d1)
23 mpp2 2 gpio, ge0(txd1), lcd(d2)
24 mpp3 3 gpio, ge0(txd2), lcd(d3)
25 mpp4 4 gpio, ge0(txd3), lcd(d4)
26 mpp5 5 gpio, ge0(txctl), lcd(d5)
[all …]
H A Dmarvell,orion-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f5181-pinctrl",
8 "marvell,88f5181l-pinctrl",
9 "marvell,88f5182-pinctrl",
10 "marvell,88f5281-pinctrl"
12 - reg: two register areas, the first one describing the first two
24 mpp0 0 pcie(rstout), pci(req2), gpio
25 mpp1 1 gpio, pci(gnt2)
26 mpp2 2 gpio, pci(req3), pci-1(pme)
27 mpp3 3 gpio, pci(gnt3)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5410-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Exynos5410 SoC pin-mux and pin-config device tree source
9 #include "exynos-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
20 gpa1: gpa1-gpio-bank {
21 gpio-controller;
[all …]
/freebsd/sys/contrib/device-tree/src/arc/
H A Dabilis_tb101.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
15 bus-frequency = <166666666>;
18 clock-frequency = <1000000000>;
21 clock-mult = <1>;
22 clock-div = <2>;
25 clock-mult = <1>;
26 clock-div = <6>;
31 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
34 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
37 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
[all …]
H A Dabilis_tb100.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
15 bus-frequency = <166666666>;
18 clock-frequency = <1000000000>;
21 clock-mult = <1>;
22 clock-div = <2>;
25 clock-mult = <1>;
26 clock-div = <6>;
31 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
34 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
37 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dfsl-imx-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/gpio/fsl-imx-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX/MXC GPIO controller
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
17 - enum:
18 - fsl,imx1-gpio
[all …]
H A Drenesas,rcar-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/renesas,rcar-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car General-Purpose Input/Output Ports (GPIO)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - items:
16 - enum:
17 - renesas,gpio-r8a7778 # R-Car M1
18 - renesas,gpio-r8a7779 # R-Car H1
[all …]
H A Dgpio.txt1 Specifying GPIO information for devices
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
23 The following example could be used to describe GPIO pins used as device enable
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
[all …]
H A Dgpio-ep9301.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-ep9301.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: EP93xx GPIO controller
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
12 - Nikita Shubin <nikita.shubin@maquefel.me>
17 - const: cirrus,ep9301-gpio
18 - items:
[all …]
H A Dnvidia,tegra186-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
20 The Tegra186 GPIO controller allows software to set the IO direction of,
21 and read/write the value of, numerous GPIO signals. Routing of GPIO signals
[all …]
H A Dnvidia,tegra186-gpio.txt1 NVIDIA Tegra186 GPIO controllers
3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
14 a) Security registers, which allow configuration of allowed access to the GPIO
17 varies between the different GPIO controllers.
20 that wishes to configure access to the GPIO registers needs access to these
21 registers to do so. Code which simply wishes to read or write GPIO data does not
24 b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
27 documentation for rationale. Any particular GPIO client is expected to access
[all …]
H A Dgpio-davinci.txt1 Davinci/Keystone GPIO controller bindings
4 - compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs
5 "ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L,
7 "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G
8 "ti,am654-gpio", "ti,keystone-gpio": for TI K3 AM654
9 "ti,j721e-gpio", "ti,keystone-gpio": for J721E SoCs
10 "ti,am64-gpio", "ti,keystone-gpio": for AM64 SoCs
12 - reg: Physical base address of the controller and the size of memory mapped
15 - gpio-controller : Marks the device node as a gpio controller.
17 - #gpio-cells : Should be two.
[all …]
H A Daspeed,ast2400-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/aspeed,ast2400-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aspeed GPIO controller
10 - Andrew Jeffery <andrew@codeconstruct.com.au>
15 - aspeed,ast2400-gpio
16 - aspeed,ast2500-gpio
17 - aspeed,ast2600-gpio
26 gpio-controller: true
[all …]
H A Dgpio-davinci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-davinci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controller for Davinci and keystone devices
10 - Keerthy <j-keerthy@ti.com>
15 - items:
16 - enum:
17 - ti,k2g-gpio
18 - ti,am654-gpio
[all …]
H A Dnxp,lpc1850-gpio.txt1 NXP LPC18xx/43xx GPIO controller Device Tree Bindings
2 -----------------------------------------------------
5 - compatible : Should be "nxp,lpc1850-gpio"
6 - reg : List of addresses and lengths of the GPIO controller
8 - reg-names : Should be "gpio", "gpio-pin-ic", "gpio-group0-ic" and
9 "gpio-gpoup1-ic"
10 - clocks : Phandle and clock specifier pair for GPIO controller
11 - resets : Phandle and reset specifier pair for GPIO controller
12 - gpio-controller : Marks the device node as a GPIO controller
13 - #gpio-cells : Should be two:
[all …]
/freebsd/sys/dev/sdhci/
H A Dsdhci_fdt_gpio.c1 /*-
27 * Support routines usable by any SoC sdhci bridge driver that uses gpio pins
33 #include <sys/gpio.h>
38 #include <dev/gpio/gpiobusvar.h>
65 struct sdhci_fdt_gpio *gpio = arg; in cd_intr() local
67 sdhci_handle_card_present(gpio->slot, sdhci_fdt_gpio_get_present(gpio)); in cd_intr()
74 cd_setup(struct sdhci_fdt_gpio *gpio, phandle_t node) in cd_setup() argument
80 dev = gpio->dev; in cd_setup()
83 * If the device is flagged as non-removable, set that slot option, and in cd_setup()
86 if (OF_hasprop(node, "non-removable")) { in cd_setup()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/tesla/
H A Dfsd-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2021 Tesla, Inc.
11 #include "fsd-pinctrl.h"
14 gpf0: gpf0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
18 interrupt-controller;
19 #interrupt-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am65-iot2050-arduino-connector.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) Siemens AG, 2018-2023
13 pinctrl-names =
15 "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown",
16 "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown",
17 "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown",
18 "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown",
19 "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown",
20 "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown",
21 "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown",
[all …]
/freebsd/sys/dts/
H A Dbindings-gpio.txt2 GPIO configuration.
5 1. Properties for GPIO Controllers
7 1.1 #gpio-cells
9 Property: #gpio-cells
13 Description: The #gpio-cells property defines the number of cells required
14 to encode a gpio specifier.
17 1.2 gpio-controller
19 Property: gpio-controller
23 Description: The presence of a gpio-controller property defines a node as a
24 GPIO controller node.
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos7-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
[all …]
H A Dexynos5433-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
32 gpa0: gpa0-gpio-bank {
33 gpio-controller;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-bmc-opp-swift.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
3 #include "aspeed-g5.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
5 #include <dt-bindings/leds/leds-pca955x.h>
9 compatible = "ibm,swift-bmc", "aspeed,ast2500";
12 stdout-path = &uart5;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]

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