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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gfx.c38 /* delay 0.1 second to enable gfx off feature */
44 * GPU GFX IP block helpers function.
52 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
53 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
54 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
63 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
64 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
65 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
66 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
67 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
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H A Dgfx_v11_0.c41 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
253 /* gfx queue registers */
353 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx11_kiq_set_resources()
418 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx11_kiq_unmap_queues()
486 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
663 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v11_0_free_microcode()
664 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v11_0_free_microcode()
665 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v11_0_free_microcode()
666 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v11_0_free_microcode()
668 kfree(adev->gfx.rlc.register_list_format); in gfx_v11_0_free_microcode()
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H A Dgfx_v6_0.c353 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v6_0_init_microcode()
358 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
359 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
360 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
362 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v6_0_init_microcode()
367 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
368 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
369 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
371 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, in gfx_v6_0_init_microcode()
376 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v6_0_init_microcode()
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H A Dgfx_v12_0.c39 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h"
208 /* gfx queue registers */
358 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx_v12_0_kiq_unmap_queues()
426 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; in gfx_v12_0_set_kiq_pm4_funcs()
557 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v12_0_free_microcode()
558 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v12_0_free_microcode()
559 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v12_0_free_microcode()
560 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v12_0_free_microcode()
562 kfree(adev->gfx.rlc.register_list_format); in gfx_v12_0_free_microcode()
600 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v12_0_init_microcode()
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H A Dgfx_v7_0.c892 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v7_0_free_microcode()
893 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v7_0_free_microcode()
894 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v7_0_free_microcode()
895 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v7_0_free_microcode()
896 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v7_0_free_microcode()
897 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v7_0_free_microcode()
939 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v7_0_init_microcode()
945 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v7_0_init_microcode()
951 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, in gfx_v7_0_init_microcode()
957 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, in gfx_v7_0_init_microcode()
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H A Dgfx_v8_0.c927 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
928 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v8_0_free_microcode()
929 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
930 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
931 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v8_0_free_microcode()
934 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v8_0_free_microcode()
936 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
984 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v8_0_init_microcode()
988 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v8_0_init_microcode()
993 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v8_0_init_microcode()
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H A Dgfx_v9_4_3.c34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
182 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx_v9_4_3_kiq_set_resources()
342 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_set_kiq_pm4_funcs()
344 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; in gfx_v9_4_3_set_kiq_pm4_funcs()
351 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_init_golden_registers()
513 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v9_4_3_get_gpu_clock_counter()
517 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v9_4_3_get_gpu_clock_counter()
524 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_4_3_free_microcode()
525 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_4_3_free_microcode()
526 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_4_3_free_microcode()
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H A Damdgpu_kms.c234 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
235 fw_info->feature = adev->gfx.me_feature_version; in amdgpu_firmware_info()
238 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
239 fw_info->feature = adev->gfx.pfp_feature_version; in amdgpu_firmware_info()
242 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
243 fw_info->feature = adev->gfx.ce_feature_version; in amdgpu_firmware_info()
246 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
247 fw_info->feature = adev->gfx.rlc_feature_version; in amdgpu_firmware_info()
250 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
251 fw_info->feature = adev->gfx.rlc_srlc_feature_version; in amdgpu_firmware_info()
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H A Damdgpu_ucode.c114 DRM_DEBUG("GFX\n"); in amdgpu_ucode_print_gfx_hdr()
132 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); in amdgpu_ucode_print_gfx_hdr()
754 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
755 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
756 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
757 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
758 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
759 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
760 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
761 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
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H A Dimu_v11_0.c56 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, in imu_v11_0_init_microcode()
59 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, in imu_v11_0_init_microcode()
64 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_init_microcode()
65 //adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version); in imu_v11_0_init_microcode()
70 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
75 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
79 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); in imu_v11_0_init_microcode()
86 amdgpu_ucode_release(&adev->gfx.imu_fw); in imu_v11_0_init_microcode()
98 if (!adev->gfx.imu_fw) in imu_v11_0_load_microcode()
101 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_load_microcode()
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H A Dimu_v12_0.c52 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, in imu_v12_0_init_microcode()
55 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, in imu_v12_0_init_microcode()
60 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v12_0_init_microcode()
61 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); in imu_v12_0_init_microcode()
66 info->fw = adev->gfx.imu_fw; in imu_v12_0_init_microcode()
71 info->fw = adev->gfx.imu_fw; in imu_v12_0_init_microcode()
81 amdgpu_ucode_release(&adev->gfx.imu_fw); in imu_v12_0_init_microcode()
93 if (!adev->gfx.imu_fw) in imu_v12_0_load_microcode()
96 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v12_0_load_microcode()
98 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v12_0_load_microcode()
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H A Damdgpu_discovery.c756 adev->gfx.xcc_mask &= in amdgpu_discovery_read_from_harvest_table()
1048 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; in amdgpu_discovery_get_harvest_info()
1345 adev->gfx.xcc_mask = 0; in amdgpu_discovery_reg_base_init()
1442 adev->gfx.xcc_mask |= in amdgpu_discovery_reg_base_init()
1597 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); in amdgpu_discovery_get_gfx_info()
1598 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + in amdgpu_discovery_get_gfx_info()
1600 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
1601 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
1602 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); in amdgpu_discovery_get_gfx_info()
1603 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); in amdgpu_discovery_get_gfx_info()
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H A Damdgpu_mes.c109 adev->mes.vmid_mask_gfxhub = adev->gfx.disable_kq ? 0xfffffffe : 0xffffff00; in amdgpu_mes_init()
111 num_pipes = adev->gfx.me.num_pipe_per_me * adev->gfx.me.num_me; in amdgpu_mes_init()
113 dev_warn(adev->dev, "more gfx pipes than supported by MES! (%d vs %d)\n", in amdgpu_mes_init()
122 * GFX V12 has only one GFX pipe, but 8 queues in it. in amdgpu_mes_init()
123 * GFX pipe 0 queue 0 is being used by Kernel queue. in amdgpu_mes_init()
124 * Set GFX pipe 0 queue 1-7 for MES scheduling in amdgpu_mes_init()
127 adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0xFF : 0xFE; in amdgpu_mes_init()
130 * GFX pipe 0 queue 0 is being used by Kernel queue. in amdgpu_mes_init()
131 * Set GFX pipe 0 queue 1 for MES scheduling in amdgpu_mes_init()
134 adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0x3 : 0x2; in amdgpu_mes_init()
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H A Damdgpu_amdkfd.c180 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, in amdgpu_amdkfd_device_init()
181 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
194 adev->gfx.mec_bitmap[0].queue_bitmap, in amdgpu_amdkfd_device_init()
201 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
202 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
446 return adev->gfx.pfp_fw_version; in amdgpu_amdkfd_get_fw_version()
449 return adev->gfx.me_fw_version; in amdgpu_amdkfd_get_fw_version()
452 return adev->gfx.ce_fw_version; in amdgpu_amdkfd_get_fw_version()
455 return adev->gfx.mec_fw_version; in amdgpu_amdkfd_get_fw_version()
458 return adev->gfx.mec2_fw_version; in amdgpu_amdkfd_get_fw_version()
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H A Daqua_vanjaram.c89 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_calc_xcp_mode()
90 if (adev->gfx.funcs->get_xccs_per_xcp) in __aqua_vanjaram_calc_xcp_mode()
91 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); in __aqua_vanjaram_calc_xcp_mode()
144 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_get_xcc_per_xcp()
179 num_xcc_xcp = adev->gfx.num_xcc_per_xcp; in __aqua_vanjaram_get_xcp_ip_info()
180 num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; in __aqua_vanjaram_get_xcp_ip_info()
258 *num_xcp = NUM_XCC(adev->gfx.xcc_mask); in __aqua_vanjaram_get_px_mode_info()
284 max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev->gfx.xcc_mask); in aqua_vanjaram_get_xcp_res_info()
319 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_get_auto_mode()
353 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in __aqua_vanjaram_is_valid_mode()
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/linux/Documentation/ABI/testing/
H A Dsysfs-driver-intel-i915-hwmon4 Contact: intel-gfx@lists.freedesktop.org
12 Contact: intel-gfx@lists.freedesktop.org
26 Contact: intel-gfx@lists.freedesktop.org
34 Contact: intel-gfx@lists.freedesktop.org
43 Contact: intel-gfx@lists.freedesktop.org
56 Contact: intel-gfx@lists.freedesktop.org
69 Contact: intel-gfx@lists.freedesktop.org
82 Contact: intel-gfx@lists.freedesktop.org
90 Contact: intel-gfx@lists.freedesktop.org
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v13_0_1_ppsmc.h55 #define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down GFX, i.e. enter GFXOFF
56 #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
61 #define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset
67 #define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency
71 #define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK
72 #define PPSMC_MSG_SetHardMinGfxClk 0x1C ///< Set hard min for GFX CLK
83 #define PPSMC_MSG_RequestActiveWgp 0x27 ///< Request GFX active WGP number
H A Dsmu_v13_0_4_ppsmc.h65 #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
70 #define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset
76 #define PPSMC_MSG_EnableGfxImu 0x16 ///< Enable GFX IMU
78 #define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency
82 #define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK
83 #define PPSMC_MSG_SetHardMinGfxClk 0x1C ///< Set hard min for GFX CLK
H A Dsmu_v13_0_5_ppsmc.h45 #define PPSMC_MSG_GfxDeviceDriverReset 10 ///< Request GFX mode 2 reset
50 #define PPSMC_MSG_GetGfxclkFrequency 15 ///< Get GFX clock frequency
56 #define PPSMC_MSG_SetHardMinGfxClk 21 ///< Set hard min for GFX CLK
61 #define PPSMC_MSG_PrepareMp1ForUnload 26 ///< Prepare PMFW for GFX driver unload
H A Dsmu11_driver_if_sienna_cichlid.h249 // GFX GPO Feature Contains PACE and DEM sub features
452 //Piecewise linear droop model, Sienna_Cichlid currently used only for GFX DFLL
655 …old; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnect…
716 // GFX GPO
731 …uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX D…
732 … DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase …
734 …inCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
737 …imeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before …
837 uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages
1015 …old; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnect…
[all …]
/linux/drivers/pmdomain/qcom/
H A Drpmhpd.c110 static struct rpmhpd gfx = { variable
111 .pd = { .name = "gfx", },
112 .res_name = "gfx.lvl",
225 [RPMHPD_GFX] = &gfx,
262 [SA8775P_GFX] = &gfx,
285 [RPMHPD_GFX] = &gfx,
308 [SDM670_GFX] = &gfx,
326 [SDM845_GFX] = &gfx,
399 [SM6350_GFX] = &gfx,
415 [RPMHPD_GFX] = &gfx,
[all …]
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_gfxpll.c15 * GFX PLL is the PLL used by DC, GMC and GPU, the structure of the GFX PLL
139 /* GFX (DC, GPU, GMC) PLL initialization and destroy function */
177 const struct loongson_gfx_desc *gfx = to_loongson_gfx(ldev->descp); in loongson_gfxpll_create() local
186 this->reg_size = gfx->gfxpll.reg_size; in loongson_gfxpll_create()
187 this->reg_base = gfx->conf_reg_base + gfx->gfxpll.reg_offset; in loongson_gfxpll_create()
/linux/drivers/gpu/drm/i915/gt/uc/abi/
H A Dguc_klvs_abi.h42 * Refers to 64 bit Global Gfx address of H2G `CT Buffer`_.
46 * Refers to 64 bit Global Gfx address of H2G `CTB Descriptor`_.
54 * Refers to 64 bit Global Gfx address of G2H `CT Buffer`_.
58 * Refers to 64 bit Global Gfx address of G2H `CTB Descriptor`_.
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gpucc.yaml59 vdd-gfx-supply:
68 # Require that power-domains and vdd-gfx-supply are not both present
72 - vdd-gfx-supply
/linux/include/uapi/drm/
H A Damdgpu_drm.h435 /* GFX V11 IP specific MQD parameters */
449 /* GFX V11 SDMA IP specific MQD parameters */
459 /* GFX V11 Compute IP specific MQD parameters */
1125 /* Subquery id: Query GFX ME firmware version */
1127 /* Subquery id: Query GFX PFP firmware version */
1129 /* Subquery id: Query GFX CE firmware version */
1131 /* Subquery id: Query GFX RLC firmware version */
1133 /* Subquery id: Query GFX MEC firmware version */
1145 /* Subquery id: Query GFX RLC SRLC firmware version */
1147 /* Subquery id: Query GFX RLC SRLG firmware version */
[all …]

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