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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_0.c35 #include "gc/gc_10_1_0_offset.h"
36 #include "gc/gc_10_1_0_sh_mask.h"
280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
283 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
[all …]
H A Dimu_v11_0.c31 #include "gc/gc_11_0_0_offset.h"
32 #include "gc/gc_11_0_0_sh_mask.h"
101 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0); in imu_v11_0_load_microcode()
104 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v11_0_load_microcode()
106 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v11_0_load_microcode()
113 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0); in imu_v11_0_load_microcode()
116 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v11_0_load_microcode()
118 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v11_0_load_microcode()
128 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); in imu_v11_0_wait_for_reset_status()
147 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff); in imu_v11_0_setup()
[all …]
H A Dimu_v11_0_3.c27 #include "gc/gc_11_0_3_offset.h"
28 #include "gc/gc_11_0_3_sh_mask.h"
31 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_RD_COMBINE_FLUSH, 0x00055555, 0xe0000000),
32 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_WR_COMBINE_FLUSH, 0x00055555, 0xe0000000),
33 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_DRAM_COMBINE_FLUSH, 0x00555555, 0xe0000000),
34 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC2, 0x00001ffe, 0xe0000000),
35 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_CREDITS, 0x003f3fff, 0xe0000000),
36 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_TAG_RESERVE1, 0x00000000, 0xe0000000),
37 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE0, 0x00041000, 0xe0000000),
38 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE1, 0x00000000, 0xe0000000),
[all …]
H A Dgfxhub_v1_2.c28 #include "gc/gc_9_4_3_offset.h"
29 #include "gc/gc_9_4_3_sh_mask.h"
39 return (u64)RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_FB_OFFSET) << 24; in gfxhub_v1_2_get_mc_fb_offset()
52 WREG32_SOC15_OFFSET(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_setup_vm_pt_regs()
57 WREG32_SOC15_OFFSET(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_setup_vm_pt_regs()
92 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
95 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
99 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
102 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
106 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
[all …]
H A Dimu_v12_0.c31 #include "gc/gc_12_0_0_offset.h"
32 #include "gc/gc_12_0_0_sh_mask.h"
96 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0); in imu_v12_0_load_microcode()
99 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v12_0_load_microcode()
101 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v12_0_load_microcode()
108 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0); in imu_v12_0_load_microcode()
111 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v12_0_load_microcode()
113 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v12_0_load_microcode()
124 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); in imu_v12_0_wait_for_reset_status()
142 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff); in imu_v12_0_setup()
[all …]
H A Dgfx_v9_4.c33 #include "gc/gc_9_4_1_offset.h"
34 #include "gc/gc_9_4_1_sh_mask.h"
42 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1 },
43 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1 },
45 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1 },
46 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1 },
47 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1 },
49 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1 },
50 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1 },
52 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1 },
[all …]
H A Dgfxhub_v2_1.c27 #include "gc/gc_10_3_0_offset.h"
28 #include "gc/gc_10_3_0_sh_mask.h"
29 #include "gc/gc_10_3_0_default.h"
110 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_1_get_fb_location()
120 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_1_get_mc_fb_offset()
128 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v2_1_setup_vm_pt_regs()
132 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v2_1_setup_vm_pt_regs()
143 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v2_1_init_gart_aperture_regs()
145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v2_1_init_gart_aperture_regs()
148 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v2_1_init_gart_aperture_regs()
[all …]
H A Dgfx_v9_4_2.c27 #include "gc/gc_9_4_2_offset.h"
28 #include "gc/gc_9_4_2_sh_mask.h"
64 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x141dc920),
65 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0x3b458b93),
66 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x1a4f5583),
67 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0x317717f6),
68 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_4, 0x3fffffff, 0x107cc1e6),
69 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_5, 0x3ff, 0x351),
73 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x2591aa38),
74 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0xac9e88b),
[all …]
H A Dgfxhub_v1_0.c27 #include "gc/gc_9_0_offset.h"
28 #include "gc/gc_9_0_sh_mask.h"
29 #include "gc/gc_9_0_default.h"
36 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; in gfxhub_v1_0_get_mc_fb_offset()
45 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v1_0_setup_vm_pt_regs()
49 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v1_0_setup_vm_pt_regs()
69 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
71 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
74 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
76 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
[all …]
H A Dgfx_v9_4_3.c36 #include "gc/gc_9_4_3_offset.h"
37 #include "gc/gc_9_4_3_sh_mask.h"
68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
[all …]
H A Dgfxhub_v2_0.c27 #include "gc/gc_10_1_0_offset.h"
28 #include "gc/gc_10_1_0_sh_mask.h"
29 #include "gc/gc_10_1_0_default.h"
107 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_0_get_fb_location()
117 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_0_get_mc_fb_offset()
125 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v2_0_setup_vm_pt_regs()
129 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v2_0_setup_vm_pt_regs()
140 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs()
142 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs()
145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs()
[all …]
H A Dgfxhub_v3_0.c27 #include "gc/gc_11_0_0_offset.h"
28 #include "gc/gc_11_0_0_sh_mask.h"
29 #include "gc/gc_11_0_0_default.h"
106 u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE); in gfxhub_v3_0_get_fb_location()
116 return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24; in gfxhub_v3_0_get_mc_fb_offset()
124 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v3_0_setup_vm_pt_regs()
128 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v3_0_setup_vm_pt_regs()
139 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v3_0_init_gart_aperture_regs()
141 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v3_0_init_gart_aperture_regs()
144 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v3_0_init_gart_aperture_regs()
[all …]
H A Dgfxhub_v11_5_0.c27 #include "gc/gc_11_5_0_offset.h"
28 #include "gc/gc_11_5_0_sh_mask.h"
111 u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE); in gfxhub_v11_5_0_get_fb_location()
121 return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24; in gfxhub_v11_5_0_get_mc_fb_offset()
129 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v11_5_0_setup_vm_pt_regs()
133 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v11_5_0_setup_vm_pt_regs()
144 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v11_5_0_init_gart_aperture_regs()
146 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v11_5_0_init_gart_aperture_regs()
149 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v11_5_0_init_gart_aperture_regs()
151 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v11_5_0_init_gart_aperture_regs()
[all …]
H A Dgfxhub_v12_0.c27 #include "gc/gc_12_0_0_offset.h"
28 #include "gc/gc_12_0_0_sh_mask.h"
113 u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE); in gfxhub_v12_0_get_fb_location()
123 return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24; in gfxhub_v12_0_get_mc_fb_offset()
132 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v12_0_setup_vm_pt_regs()
136 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v12_0_setup_vm_pt_regs()
147 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v12_0_init_gart_aperture_regs()
149 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v12_0_init_gart_aperture_regs()
152 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v12_0_init_gart_aperture_regs()
154 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v12_0_init_gart_aperture_regs()
[all …]
H A Dgfx_v9_0.c37 #include "gc/gc_9_0_offset.h"
38 #include "gc/gc_9_0_sh_mask.h"
58 #include "asic_reg/gc/gc_9_0_default.h"
154 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
155 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
156 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
157 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
158 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
159 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
160 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
[all …]
/linux/drivers/gpio/
H A Dgpio-mmio.c124 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line) in bgpio_line2mask() argument
126 if (gc->be_bits) in bgpio_line2mask()
127 return BIT(gc->bgpio_bits - 1 - line); in bgpio_line2mask()
131 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) in bgpio_get_set() argument
133 unsigned long pinmask = bgpio_line2mask(gc, gpio); in bgpio_get_set()
134 bool dir = !!(gc->bgpio_dir & pinmask); in bgpio_get_set()
137 return !!(gc->read_reg(gc->reg_set) & pinmask); in bgpio_get_set()
139 return !!(gc->read_reg(gc->reg_dat) & pinmask); in bgpio_get_set()
146 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, in bgpio_get_set_multiple() argument
155 set_mask = *mask & gc->bgpio_dir; in bgpio_get_set_multiple()
[all …]
H A Dgpiolib.c95 static void gpiochip_free_hogs(struct gpio_chip *gc);
96 static int gpiochip_add_irqchip(struct gpio_chip *gc,
99 static void gpiochip_irqchip_remove(struct gpio_chip *gc);
100 static int gpiochip_irqchip_init_hw(struct gpio_chip *gc);
101 static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gc);
102 static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gc);
176 struct gpio_desc *gpiochip_get_desc(struct gpio_chip *gc, in gpiochip_get_desc() argument
179 return gpio_device_get_desc(gc->gpiodev, hwnum); in gpiochip_get_desc()
367 if (!guard.gc) in gpiod_get_direction()
381 if (!guard.gc->get_direction) in gpiod_get_direction()
[all …]
H A Dgpio-reg.c22 struct gpio_chip gc; member
31 #define to_gpio_reg(x) container_of(x, struct gpio_reg, gc)
33 static int gpio_reg_get_direction(struct gpio_chip *gc, unsigned offset) in gpio_reg_get_direction() argument
35 struct gpio_reg *r = to_gpio_reg(gc); in gpio_reg_get_direction()
41 static int gpio_reg_direction_output(struct gpio_chip *gc, unsigned offset, in gpio_reg_direction_output() argument
44 struct gpio_reg *r = to_gpio_reg(gc); in gpio_reg_direction_output()
49 gc->set(gc, offset, value); in gpio_reg_direction_output()
53 static int gpio_reg_direction_input(struct gpio_chip *gc, unsigned offset) in gpio_reg_direction_input() argument
55 struct gpio_reg *r = to_gpio_reg(gc); in gpio_reg_direction_input()
60 static void gpio_reg_set(struct gpio_chip *gc, unsigned offset, int value) in gpio_reg_set() argument
[all …]
H A Dgpio-mpc8xxx.c38 struct gpio_chip gc; member
64 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) in mpc8572_gpio_get() argument
67 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); in mpc8572_gpio_get()
70 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); in mpc8572_gpio_get()
71 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; in mpc8572_gpio_get()
72 out_shadow = gc->bgpio_data & out_mask; in mpc8572_gpio_get()
77 static int mpc5121_gpio_dir_out(struct gpio_chip *gc, in mpc5121_gpio_dir_out() argument
80 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); in mpc5121_gpio_dir_out()
85 return mpc8xxx_gc->direction_output(gc, gpio, val); in mpc5121_gpio_dir_out()
88 static int mpc5125_gpio_dir_out(struct gpio_chip *gc, in mpc5125_gpio_dir_out() argument
[all …]
/linux/kernel/irq/
H A Dgeneric-chip.c39 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); in irq_gc_mask_disable_reg() local
43 irq_gc_lock(gc); in irq_gc_mask_disable_reg()
44 irq_reg_writel(gc, mask, ct->regs.disable); in irq_gc_mask_disable_reg()
46 irq_gc_unlock(gc); in irq_gc_mask_disable_reg()
55 * and protected by gc->lock
59 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); in irq_gc_mask_set_bit() local
63 irq_gc_lock(gc); in irq_gc_mask_set_bit()
65 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); in irq_gc_mask_set_bit()
66 irq_gc_unlock(gc); in irq_gc_mask_set_bit()
75 * and protected by gc->lock
[all …]
/linux/drivers/irqchip/
H A Dirq-atmel-aic.c62 struct irq_domain_chip_generic *dgc = aic_domain->gc; in aic_handle()
63 struct irq_chip_generic *gc = dgc->gc[0]; in aic_handle() local
67 irqnr = irq_reg_readl(gc, AT91_AIC_IVR); in aic_handle()
68 irqstat = irq_reg_readl(gc, AT91_AIC_ISR); in aic_handle()
71 irq_reg_writel(gc, 0, AT91_AIC_EOICR); in aic_handle()
78 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); in aic_retrigger() local
81 irq_gc_lock(gc); in aic_retrigger()
82 irq_reg_writel(gc, d->mask, AT91_AIC_ISCR); in aic_retrigger()
83 irq_gc_unlock(gc); in aic_retrigger()
90 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); in aic_set_type() local
[all …]
H A Dirq-tb10x.c30 static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg, in ab_irqctl_writereg() argument
33 irq_reg_writel(gc, val, reg); in ab_irqctl_writereg()
36 static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg) in ab_irqctl_readreg() argument
38 return irq_reg_readl(gc, reg); in ab_irqctl_readreg()
43 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); in tb10x_irq_set_type() local
48 irq_gc_lock(gc); in tb10x_irq_set_type()
50 mod = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) | im; in tb10x_irq_set_type()
51 pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im; in tb10x_irq_set_type()
70 irq_gc_unlock(gc); in tb10x_irq_set_type()
79 ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod); in tb10x_irq_set_type()
[all …]
H A Dirq-sunxi-nmi.c75 static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off, in sunxi_sc_nmi_write() argument
78 irq_reg_writel(gc, val, off); in sunxi_sc_nmi_write()
81 static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off) in sunxi_sc_nmi_read() argument
83 return irq_reg_readl(gc, off); in sunxi_sc_nmi_read()
98 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); in sunxi_sc_nmi_set_type() local
99 struct irq_chip_type *ct = gc->chip_types; in sunxi_sc_nmi_set_type()
105 irq_gc_lock(gc); in sunxi_sc_nmi_set_type()
122 irq_gc_unlock(gc); in sunxi_sc_nmi_set_type()
131 for (i = 0; i < gc->num_ct; i++, ct++) in sunxi_sc_nmi_set_type()
135 src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off); in sunxi_sc_nmi_set_type()
[all …]
/linux/drivers/net/ethernet/microsoft/mana/
H A Dgdma_main.c23 struct gdma_context *gc = pci_get_drvdata(pdev); in mana_gd_init_pf_regs() local
27 gc->db_page_size = mana_gd_r32(gc, GDMA_PF_REG_DB_PAGE_SIZE) & 0xFFFF; in mana_gd_init_pf_regs()
28 gc->db_page_base = gc->bar0_va + in mana_gd_init_pf_regs()
29 mana_gd_r64(gc, GDMA_PF_REG_DB_PAGE_OFF); in mana_gd_init_pf_regs()
31 sriov_base_off = mana_gd_r64(gc, GDMA_SRIOV_REG_CFG_BASE_OFF); in mana_gd_init_pf_regs()
33 sriov_base_va = gc->bar0_va + sriov_base_off; in mana_gd_init_pf_regs()
34 gc->shm_base = sriov_base_va + in mana_gd_init_pf_regs()
35 mana_gd_r64(gc, sriov_base_off + GDMA_PF_REG_SHM_OFF); in mana_gd_init_pf_regs()
40 struct gdma_context *gc = pci_get_drvdata(pdev); in mana_gd_init_vf_regs() local
42 gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF; in mana_gd_init_vf_regs()
[all …]
/linux/drivers/input/joystick/
H A Dgamecon.c70 struct gc { struct
84 static struct gc *gc_base[3]; argument
130 static void gc_n64_send_command(struct gc *gc, unsigned long cmd, in gc_n64_send_command() argument
133 struct parport *port = gc->pd->port; in gc_n64_send_command()
144 static void gc_n64_send_stop_bit(struct gc *gc, unsigned char target) in gc_n64_send_stop_bit() argument
146 struct parport *port = gc->pd->port; in gc_n64_send_stop_bit()
162 static void gc_n64_read_packet(struct gc *gc, unsigned char *data) in gc_n64_read_packet() argument
172 gc_n64_send_command(gc, GC_N64_REQUEST_DATA, GC_N64_OUT); in gc_n64_read_packet()
173 gc_n64_send_stop_bit(gc, GC_N64_OUT); in gc_n64_read_packet()
188 parport_write_data(gc->pd->port, GC_N64_POWER_R); in gc_n64_read_packet()
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