Home
last modified time | relevance | path

Searched full:gateable (Results 1 – 12 of 12) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-osc-clk.yaml7 title: Allwinner A10 Gateable Oscillator Clock
/linux/Documentation/arch/arm/sunxi/
H A Dclocks.rst8 Q: Why is the main 24MHz oscillator gateable? Wouldn't that break the
/linux/Documentation/devicetree/bindings/bus/
H A Drenesas,bsc.yaml19 PM domain, and may have a gateable functional clock. Before a device
/linux/drivers/clk/mvebu/
H A Dcp110-system-controller.c24 * CP110 has 32 gateable clocks, for the various peripherals in the IP.
60 /* A number of gateable clocks need special handling */
H A Dcommon.c246 pr_err("mvebu-clk-gating: cannot instantiate more than one gateable clock device\n"); in mvebu_clk_gating_setup()
/linux/drivers/clk/imx/
H A Dclk-gate2.c19 * DOC: basic gateable clock which can gate and ungate its output
/linux/drivers/clk/
H A Dclk-gate.c18 * DOC: basic gateable clock which can gate and ungate its output
H A Dclk-gpio.c255 * struct clk_gated_fixed - Gateable fixed rate clock
/linux/drivers/thermal/ti-soc-thermal/
H A Dti-bandgap.h268 * device are gateable or not.
/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c877 u8 gate; /* is it independently gateable? */
/linux/scripts/
H A Dspelling.txt767 gatable||gateable
/linux/drivers/mtd/nand/raw/brcmnand/
H A Dbrcmnand.c253 /* Some SoCs have a gateable clock for the controller */