| /linux/drivers/clk/mxs/ |
| H A D | clk-frac.c | 36 struct clk_frac *frac = to_clk_frac(hw); in clk_frac_recalc_rate() local
40 div = readl_relaxed(frac->reg) >> frac->shift; in clk_frac_recalc_rate()
41 div &= (1 << frac->width) - 1; in clk_frac_recalc_rate()
44 return tmp_rate >> frac->width; in clk_frac_recalc_rate()
50 struct clk_frac *frac = to_clk_frac(hw); in clk_frac_determine_rate() local
59 tmp <<= frac->width; in clk_frac_determine_rate()
67 result = tmp_rate >> frac->width; in clk_frac_determine_rate()
68 if ((result << frac->width) < tmp_rate) in clk_frac_determine_rate()
78 struct clk_frac *frac = to_clk_frac(hw); in clk_frac_set_rate() local
87 tmp <<= frac->width; in clk_frac_set_rate()
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| H A D | clk-ref.c | 21 * as pll rate * (18 / FRAC), where FRAC = 18 ~ 35.
52 u8 frac = (readl_relaxed(ref->reg) >> (ref->idx * 8)) & 0x3f; in clk_ref_recalc_rate() local
55 do_div(tmp, frac); in clk_ref_recalc_rate()
65 u8 frac; in clk_ref_determine_rate() local
69 frac = clamp(tmp, 18, 35); in clk_ref_determine_rate()
73 do_div(tmp, frac); in clk_ref_determine_rate()
87 u8 frac, shift = ref->idx * 8; in clk_ref_set_rate() local
91 frac = clamp(tmp, 18, 35); in clk_ref_set_rate()
97 val |= frac << shift; in clk_ref_set_rate()
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| H A D | clk-imx23.c | 35 #define FRAC (CLKCTRL + 0x00f0) macro
54 /* SAIF has to use frac div for functional operation */ in clk_misc_init()
67 * so set frac to get a 288 MHz ref_io. in clk_misc_init()
69 writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR); in clk_misc_init()
70 writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET); in clk_misc_init()
114 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); in mx23_clocks_init()
115 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); in mx23_clocks_init()
116 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); in mx23_clocks_init()
117 clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); in mx23_clocks_init()
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| /linux/drivers/clk/spear/ |
| H A D | clk-frac-synth.c | 9 #define pr_fmt(fmt) "clk-frac-synth: " fmt
44 struct clk_frac *frac = to_clk_frac(hw); in frac_calc_rate() local
45 struct frac_rate_tbl *rtbl = frac->rtbl; in frac_calc_rate()
58 struct clk_frac *frac = to_clk_frac(hw); in clk_frac_determine_rate() local
62 frac_calc_rate, frac->rtbl_cnt, &unused); in clk_frac_determine_rate()
70 struct clk_frac *frac = to_clk_frac(hw); in clk_frac_recalc_rate() local
74 if (frac->lock) in clk_frac_recalc_rate()
75 spin_lock_irqsave(frac->lock, flags); in clk_frac_recalc_rate()
77 val = readl_relaxed(frac->reg); in clk_frac_recalc_rate()
79 if (frac->lock) in clk_frac_recalc_rate()
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| /linux/drivers/clk/at91/ |
| H A D | clk-sam9x60-pll.c | 40 u32 frac; member
75 struct sam9x60_frac *frac = to_sam9x60_frac(core); in sam9x60_frac_pll_recalc_rate() local
78 freq = parent_rate * (frac->mul + 1) + in sam9x60_frac_pll_recalc_rate()
79 DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22)); in sam9x60_frac_pll_recalc_rate()
89 struct sam9x60_frac *frac = to_sam9x60_frac(core); in sam9x60_frac_pll_set() local
103 (cmul == frac->mul && cfrac == frac->frac)) in sam9x60_frac_pll_set()
111 (frac->mul << core->layout->mul_shift) | in sam9x60_frac_pll_set()
112 (frac->frac << core->layout->frac_shift)); in sam9x60_frac_pll_set()
192 struct sam9x60_frac *frac = to_sam9x60_frac(core); in sam9x60_frac_pll_compute_mul_frac() local
223 frac->mul = nmul - 1; in sam9x60_frac_pll_compute_mul_frac()
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| H A D | clk-audio-pll.c | 10 * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of
11 * its own parent. PMC and PAD can then divide the FRAC rate to best match the
14 * Traits of FRAC clock:
84 struct clk_audio_frac *frac = to_clk_audio_frac(hw); in clk_audio_pll_frac_enable() local
86 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_enable()
88 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_enable()
91 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL1, in clk_audio_pll_frac_enable()
92 AT91_PMC_AUDIO_PLL_FRACR_MASK, frac->fracr); in clk_audio_pll_frac_enable()
98 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_enable()
102 AT91_PMC_AUDIO_PLL_ND(frac->nd)); in clk_audio_pll_frac_enable()
[all …]
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| /linux/drivers/clk/imx/ |
| H A D | clk-pfdv2.c | 84 u8 frac; in clk_pfdv2_recalc_rate() local
86 frac = (readl_relaxed(pfd->reg) >> pfd->frac_off) in clk_pfdv2_recalc_rate()
89 if (!frac) { in clk_pfdv2_recalc_rate()
90 pr_debug("clk_pfdv2: %s invalid pfd frac value 0\n", in clk_pfdv2_recalc_rate()
96 do_div(tmp, frac); in clk_pfdv2_recalc_rate()
112 u8 frac; in clk_pfdv2_determine_rate() local
119 frac = tmp; in clk_pfdv2_determine_rate()
121 if (frac < 12) in clk_pfdv2_determine_rate()
122 frac = 12; in clk_pfdv2_determine_rate()
123 else if (frac > 35) in clk_pfdv2_determine_rate()
[all …]
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| H A D | clk-pfd.c | 57 u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f; in clk_pfd_recalc_rate() local
60 do_div(tmp, frac); in clk_pfd_recalc_rate()
69 u8 frac; in clk_pfd_determine_rate() local
73 frac = tmp; in clk_pfd_determine_rate()
74 if (frac < 12) in clk_pfd_determine_rate()
75 frac = 12; in clk_pfd_determine_rate()
76 else if (frac > 35) in clk_pfd_determine_rate()
77 frac = 35; in clk_pfd_determine_rate()
80 do_div(tmp, frac); in clk_pfd_determine_rate()
92 u8 frac; in clk_pfd_set_rate() local
[all …]
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | colorspaces-details.rst | 61 L = -\left( \frac{L' - 0.099}{-1.099} \right) ^{\frac{1}{0.45}} \text{, for } L' \le -0.081
63 L = \frac{L'}{4.5} \text{, for } -0.081 < L' < 0.081
65 L = \left(\frac{L' + 0.099}{1.099}\right)^{\frac{1}{0.45} } \text{, for } L' \ge 0.081
137 L = -\left( \frac{L' - 0.099}{-1.099} \right)^\frac{1}{0.45} \text{, for } L' \le -0.081
139 L = \frac{L'}{4.5}\text{, for } -0.081 < L' < 0.081
141 L = \left(\frac{L' + 0.099}{1.099}\right)^{\frac{1}{0.45} } \text{, for } L' \ge 0.081
174 Y' = \frac{219}{256} * (0.2126R' + 0.7152G' + 0.0722B') + \frac{16}{256}
176 Cb = \frac{224}{256} * (-0.1146R' - 0.3854G' + 0.5B')
178 Cr = \frac{224}{256} * (0.5R' - 0.4542G' - 0.0458B')
187 Y' = \frac{219}{256} * (0.2990R' + 0.5870G' + 0.1140B') + \frac{16}{256}
[all …]
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| /linux/drivers/gpu/drm/meson/ |
| H A D | meson_vclk.c | 491 unsigned int frac, unsigned int od1, in meson_hdmi_pll_set_params() argument
498 if (frac) in meson_hdmi_pll_set_params()
500 0x00004000 | frac); in meson_hdmi_pll_set_params()
519 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac); in meson_hdmi_pll_set_params()
542 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac); in meson_hdmi_pll_set_params()
547 if (frac < 0x10000) { in meson_hdmi_pll_set_params()
643 unsigned int frac; in meson_hdmi_pll_get_frac() local
646 /* The GXBB PLL has a /2 pre-multiplier and a larger FRAC width */ in meson_hdmi_pll_get_frac()
660 frac = mul_u64_u64_div_u64(pll_freq, frac_max, parent_freq); in meson_hdmi_pll_get_frac()
662 if (frac_m > frac) in meson_hdmi_pll_get_frac()
[all …]
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| /linux/drivers/clk/rockchip/ |
| H A D | clk.c | 146 struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb); in rockchip_clk_frac_notifier_cb() local
147 struct clk_mux *frac_mux = &frac->mux; in rockchip_clk_frac_notifier_cb()
153 frac->rate_change_idx = in rockchip_clk_frac_notifier_cb()
154 frac->mux_ops->get_parent(&frac_mux->hw); in rockchip_clk_frac_notifier_cb()
155 if (frac->rate_change_idx != frac->mux_frac_idx) { in rockchip_clk_frac_notifier_cb()
156 frac->mux_ops->set_parent(&frac_mux->hw, in rockchip_clk_frac_notifier_cb()
157 frac->mux_frac_idx); in rockchip_clk_frac_notifier_cb()
158 frac->rate_change_remuxed = 1; in rockchip_clk_frac_notifier_cb()
167 if (frac->rate_change_remuxed) { in rockchip_clk_frac_notifier_cb()
168 frac->mux_ops->set_parent(&frac_mux->hw, in rockchip_clk_frac_notifier_cb()
[all …]
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| H A D | clk-pll.c | 165 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT) in rockchip_rk3036_pll_get_params()
183 u64 frac_rate64 = prate * cur.frac; in rockchip_rk3036_pll_recalc_rate()
206 …s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", in rockchip_rk3036_pll_set_params()
208 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3036_pll_set_params()
239 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; in rockchip_rk3036_pll_set_params()
325 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", in rockchip_rk3036_pll_init()
327 cur.dsmpd, cur.frac); in rockchip_rk3036_pll_init()
328 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", in rockchip_rk3036_pll_init()
330 rate->dsmpd, rate->frac); in rockchip_rk3036_pll_init()
335 (!cur.dsmpd && (rate->frac != cur.frac))) { in rockchip_rk3036_pll_init()
[all …]
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| /linux/arch/sh/kernel/cpu/sh2a/ |
| H A D | fpu.c | 202 int frac; in denormal_subf1() local
215 frac = (ix & 0x007fffff) | 0x00800000; in denormal_subf1()
216 frac -= iy; in denormal_subf1()
217 while (frac < 0x00800000) { in denormal_subf1()
219 return frac; in denormal_subf1()
220 frac <<= 1; in denormal_subf1()
223 return (exp << 23) | (frac & 0x007fffff); in denormal_subf1()
229 int frac; in denormal_addf1() local
242 frac = (ix & 0x007fffff) | 0x00800000; in denormal_addf1()
243 frac += iy; in denormal_addf1()
[all …]
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| /linux/drivers/clk/starfive/ |
| H A D | clk-starfive-jh7110-pll.c | 16 * NF: fractional frequency dividing ratio, set by frac[23:0]. NF = frac[23:0] / 2^24 = 0 ~ 0.999.
82 u32 frac; /* frac value should be decimals multiplied by 2^24 */ member
96 unsigned int frac; member
119 .frac = JH7110_PLL##_idx##_FRAC_OFFSET, \
150 u32 frac; member
291 regmap_read(regmap, info->offsets.frac, &val); in jh7110_pll_regvals_get()
292 ret->frac = (val & JH7110_PLL_FRAC_MASK) >> JH7110_PLL_FRAC_SHIFT; in jh7110_pll_regvals_get()
310 * dacpd = dsmpd = 1: integer mode, frac value ignored in jh7110_pll_recalc_rate()
312 * rate = parent * (fbdiv + frac/2^24) / prediv / 2^postdiv1 in jh7110_pll_recalc_rate()
313 * = (parent * fbdiv + parent * frac / 2^24) / (prediv * 2^postdiv1) in jh7110_pll_recalc_rate()
[all …]
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| /linux/arch/mips/ath79/ |
| H A D | clock.c | 213 u32 frac, u32 out_div) in ar934x_get_pll_freq() argument
225 do_div(t, ref_div * frac); in ar934x_get_pll_freq()
238 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
263 frac = 1 << 18; in ar934x_clocks_init()
274 frac = 1 << 6; in ar934x_clocks_init()
278 nfrac, frac, out_div); in ar934x_clocks_init()
290 frac = 1 << 18; in ar934x_clocks_init()
301 frac = 1 << 10; in ar934x_clocks_init()
305 nfrac, frac, out_div); in ar934x_clocks_init()
356 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; in qca953x_clocks_init() local
[all …]
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| /linux/drivers/net/ethernet/marvell/mvpp2/ |
| H A D | mvpp2_tai.c | 104 static void mvpp2_tai_write_tlv(const struct timespec64 *ts, u32 frac, in mvpp2_tai_write_tlv() argument
112 mvpp2_tai_write(frac >> 16, base + MVPP22_TAI_TLV_FRAC_HIGH); in mvpp2_tai_write_tlv()
113 mvpp2_tai_write(frac, base + MVPP22_TAI_TLV_FRAC_LOW); in mvpp2_tai_write_tlv()
170 s32 frac; in mvpp22_tai_adjfine() local
187 frac = -val; in mvpp22_tai_adjfine()
192 frac = val; in mvpp22_tai_adjfine()
197 mvpp2_tai_write(frac >> 16, base + MVPP22_TAI_TLV_FRAC_HIGH); in mvpp22_tai_adjfine()
198 mvpp2_tai_write(frac, base + MVPP22_TAI_TLV_FRAC_LOW); in mvpp22_tai_adjfine()
314 u32 nano, frac; in mvpp22_tai_set_step() local
317 frac = lower_32_bits(tai->period); in mvpp22_tai_set_step()
[all …]
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| /linux/drivers/clk/x86/ |
| H A D | clk-cgu-pll.c | 22 * rate = (prate * mult + (prate * frac) / frac_div) / div
26 unsigned int div, unsigned int frac, unsigned int frac_div) in lgm_pll_calc_rate() argument
32 frate = rate64 * frac; in lgm_pll_calc_rate()
43 unsigned int div, mult, frac; in lgm_pll_recalc_rate() local
47 frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24); in lgm_pll_recalc_rate()
52 return lgm_pll_calc_rate(prate, mult, div, frac, BIT(24)); in lgm_pll_recalc_rate()
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| /linux/kernel/locking/ |
| H A D | qspinlock_stat.h | 70 u64 frac = 0; in lockevent_read() local
73 frac = 100ULL * do_div(sum, kicks); in lockevent_read()
74 frac = DIV_ROUND_CLOSEST_ULL(frac, kicks); in lockevent_read()
81 sum, frac); in lockevent_read()
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| /linux/drivers/clk/qcom/ |
| H A D | clk-rcg2.c | 891 const struct frac_entry *frac; in clk_edp_pixel_set_rate() local
899 frac = frac_table_810m; in clk_edp_pixel_set_rate()
901 frac = frac_table_675m; in clk_edp_pixel_set_rate()
903 for (; frac->num; frac++) { in clk_edp_pixel_set_rate()
905 request *= frac->den; in clk_edp_pixel_set_rate()
906 request = div_s64(request, frac->num); in clk_edp_pixel_set_rate()
916 f.m = frac->num; in clk_edp_pixel_set_rate()
917 f.n = frac->den; in clk_edp_pixel_set_rate()
937 const struct frac_entry *frac; in clk_edp_pixel_determine_rate() local
949 frac = frac_table_810m; in clk_edp_pixel_determine_rate()
[all …]
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| /linux/drivers/clk/sunxi-ng/ |
| H A D | ccu-sun8i-a23.c | 78 BIT(24), /* frac enable */
79 BIT(25), /* frac select */
80 270000000, /* frac rate 0 */
81 297000000, /* frac rate 1 */
90 BIT(24), /* frac enable */
91 BIT(25), /* frac select */
92 270000000, /* frac rate 0 */
93 297000000, /* frac rate 1 */
120 BIT(24), /* frac enable */
121 BIT(25), /* frac select */
[all …]
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| H A D | ccu-sun50i-a64.c | 77 BIT(24), /* frac enable */
78 BIT(25), /* frac select */
79 270000000, /* frac rate 0 */
80 297000000, /* frac rate 1 */
89 BIT(24), /* frac enable */
90 BIT(25), /* frac select */
91 270000000, /* frac rate 0 */
92 297000000, /* frac rate 1 */
140 BIT(24), /* frac enable */
141 BIT(25), /* frac select */
[all …]
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| H A D | ccu-sun8i-a33.c | 76 BIT(24), /* frac enable */
77 BIT(25), /* frac select */
78 270000000, /* frac rate 0 */
79 297000000, /* frac rate 1 */
88 BIT(24), /* frac enable */
89 BIT(25), /* frac select */
90 270000000, /* frac rate 0 */
91 297000000, /* frac rate 1 */
118 BIT(24), /* frac enable */
119 BIT(25), /* frac select */
[all …]
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| /linux/drivers/clk/zynqmp/ |
| H A D | pll.c | 59 pr_debug("%s() PLL get frac mode failed for %s, ret = %d\n", in zynqmp_pll_get_mode()
87 pr_debug("%s() PLL set frac mode failed for %s, ret = %d\n", in zynqmp_pll_set_mode()
139 unsigned long rate, frac; in zynqmp_pll_recalc_rate() local
159 frac = (parent_rate * data) / FRAC_DIV; in zynqmp_pll_recalc_rate()
160 rate = rate + frac; in zynqmp_pll_recalc_rate()
183 long rate_div, frac, m, f; in zynqmp_pll_set_rate() local
194 frac = (parent_rate * f) / FRAC_DIV; in zynqmp_pll_set_rate()
205 return rate + frac; in zynqmp_pll_set_rate()
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| /linux/drivers/phy/st/ |
| H A D | phy-stm32-usbphyc.c | 133 u16 frac; member
207 unsigned long long fvco, ndiv, frac; in stm32_usbphyc_get_pll_params() local
225 frac = fvco * (1 << 16); in stm32_usbphyc_get_pll_params()
226 do_div(frac, (clk_rate * 2)); in stm32_usbphyc_get_pll_params()
227 frac = frac - (ndiv * (1 << 16)); in stm32_usbphyc_get_pll_params()
228 pll_params->frac = (u16)frac; in stm32_usbphyc_get_pll_params()
235 u32 ndiv, frac; in stm32_usbphyc_pll_init() local
247 frac = FIELD_PREP(PLLFRACIN, pll_params.frac); in stm32_usbphyc_pll_init()
251 if (pll_params.frac) in stm32_usbphyc_pll_init()
252 usbphyc_pll |= PLLFRACCTL | frac; in stm32_usbphyc_pll_init()
[all …]
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| /linux/drivers/gpu/drm/imx/dc/ |
| H A D | dc-fl.c | 57 static void dc_fl_set_fmt(struct dc_fu *fu, enum dc_fu_frac frac, in dc_fl_set_fmt() argument
62 dc_fu_set_src_bpp(fu, frac, format->cpp[0] * 8); in dc_fl_set_fmt()
64 regmap_write_bits(fu->reg_cfg, LAYERPROPERTY(frac), in dc_fl_set_fmt()
71 regmap_write(fu->reg_cfg, COLORCOMPONENTBITS(frac), bits); in dc_fl_set_fmt()
72 regmap_write(fu->reg_cfg, COLORCOMPONENTSHIFT(frac), shifts); in dc_fl_set_fmt()
|